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Message-Id: <20200613083813.2027186-5-noltari@gmail.com>
Date: Sat, 13 Jun 2020 10:38:08 +0200
From: Álvaro Fernández Rojas
<noltari@...il.com>
To: p.zabel@...gutronix.de, robh+dt@...nel.org,
tsbogend@...ha.franken.de, f.fainelli@...il.com,
jonas.gorski@...il.com, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-mips@...r.kernel.org,
bcm-kernel-feedback-list@...adcom.com
Cc: Álvaro Fernández Rojas
<noltari@...il.com>
Subject: [PATCH v4 4/9] mips: bmips: dts: add BCM6328 reset controller support
BCM6328 SoCs have a reset controller for certain components.
Signed-off-by: Álvaro Fernández Rojas <noltari@...il.com>
Acked-by: Florian Fainelli <f.fainelli@...il.com>
---
v4: no changes.
v3: add reset controller definitions header file.
v2: no changes.
arch/mips/boot/dts/brcm/bcm6328.dtsi | 6 ++++++
include/dt-bindings/reset/bcm6328-reset.h | 18 ++++++++++++++++++
2 files changed, 24 insertions(+)
create mode 100644 include/dt-bindings/reset/bcm6328-reset.h
diff --git a/arch/mips/boot/dts/brcm/bcm6328.dtsi b/arch/mips/boot/dts/brcm/bcm6328.dtsi
index af860d06def6..590118cf5c12 100644
--- a/arch/mips/boot/dts/brcm/bcm6328.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi
@@ -57,6 +57,12 @@ clkctl: clock-controller@...00004 {
#clock-cells = <1>;
};
+ periph_rst: reset-controller@...00010 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x10000010 0x4>;
+ #reset-cells = <1>;
+ };
+
periph_intc: interrupt-controller@...00020 {
compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x10>,
diff --git a/include/dt-bindings/reset/bcm6328-reset.h b/include/dt-bindings/reset/bcm6328-reset.h
new file mode 100644
index 000000000000..0f3df87d47af
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6328-reset.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6328_H
+#define __DT_BINDINGS_RESET_BCM6328_H
+
+#define BCM6328_RST_SPI 0
+#define BCM6328_RST_EPHY 1
+#define BCM6328_RST_SAR 2
+#define BCM6328_RST_ENETSW 3
+#define BCM6328_RST_USBS 4
+#define BCM6328_RST_USBH 5
+#define BCM6328_RST_PCM 6
+#define BCM6328_RST_PCIE_CORE 7
+#define BCM6328_RST_PCIE 8
+#define BCM6328_RST_PCIE_EXT 9
+#define BCM6328_RST_PCIE_HARD 10
+
+#endif /* __DT_BINDINGS_RESET_BCM6328_H */
--
2.27.0
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