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Message-ID: <CAPDyKFr8Ge617QchXG1cMgZUvPZ+fRUpJamv173h1faz7-0baw@mail.gmail.com>
Date: Tue, 16 Jun 2020 13:32:15 +0200
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Pradeep P V K <ppvk@...eaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@...aro.org>,
Adrian Hunter <adrian.hunter@...el.com>,
Rob Herring <robh+dt@...nel.org>,
Veerabhadrarao Badiganti <vbadigan@...eaurora.org>,
Stephen Boyd <sboyd@...nel.org>,
Georgi Djakov <georgi.djakov@...aro.org>,
Matthias Kaehlcke <mka@...omium.org>,
"linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-arm-msm <linux-arm-msm@...r.kernel.org>,
DTML <devicetree@...r.kernel.org>,
linux-mmc-owner@...r.kernel.org,
Rajendra Nayak <rnayak@...eaurora.org>, sibis@...eaurora.org,
matthias@...omium.org
Subject: Re: [PATCH V4 2/2] dt-bindings: mmc: sdhci-msm: Add interconnect BW
scaling strings
On Tue, 9 Jun 2020 at 10:38, Pradeep P V K <ppvk@...eaurora.org> wrote:
>
> Add interconnect bandwidth scaling supported strings for qcom-sdhci
> controller.
>
> Signed-off-by: Pradeep P V K <ppvk@...eaurora.org>
> Acked-by: Rob Herring <robh@...nel.org>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@...aro.org>
Applied for next, thanks!
Kind regards
Uffe
> ---
> Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> index b8e1d2b..3b602fd 100644
> --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> @@ -54,6 +54,21 @@ Required properties:
> - qcom,dll-config: Chipset and Platform specific value. Use this field to
> specify the DLL_CONFIG register value as per Hardware Programming Guide.
>
> +Optional Properties:
> +* Following bus parameters are required for interconnect bandwidth scaling:
> +- interconnects: Pairs of phandles and interconnect provider specifier
> + to denote the edge source and destination ports of
> + the interconnect path.
> +
> +- interconnect-names: For sdhc, we have two main paths.
> + 1. Data path : sdhc to ddr
> + 2. Config path : cpu to sdhc
> + For Data interconnect path the name supposed to be
> + is "sdhc-ddr" and for config interconnect path it is
> + "cpu-sdhc".
> + Please refer to Documentation/devicetree/bindings/
> + interconnect/ for more details.
> +
> Example:
>
> sdhc_1: sdhci@...24900 {
> @@ -71,6 +86,9 @@ Example:
>
> clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
> clock-names = "core", "iface";
> + interconnects = <&qnoc MASTER_SDCC_ID &qnoc SLAVE_DDR_ID>,
> + <&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>;
> + interconnect-names = "sdhc-ddr","cpu-sdhc";
>
> qcom,dll-config = <0x000f642c>;
> qcom,ddr-config = <0x80040868>;
> --
> 1.9.1
>
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