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Message-ID: <159242503203.62212.1690942414916053920@swboyd.mtv.corp.google.com>
Date: Wed, 17 Jun 2020 13:17:12 -0700
From: Stephen Boyd <swboyd@...omium.org>
To: Alexandru Elisei <alexandru.elisei@....com>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc: mark.rutland@....com, Julien Thierry <julien.thierry@....com>,
Peter Zijlstra <peterz@...radead.org>, maz@...nel.org,
Jiri Olsa <jolsa@...hat.com>,
Will Deacon <will.deacon@....com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Ingo Molnar <mingo@...hat.com>, catalin.marinas@....com,
Namhyung Kim <namhyung@...nel.org>, will@...nel.org
Subject: Re: [PATCH v5 3/7] arm64: perf: Remove PMU locking
Quoting Alexandru Elisei (2020-06-17 04:38:47)
> From: Julien Thierry <julien.thierry@....com>
>
> The PMU is disabled and enabled, and the counters are programmed from
> contexts where interrupts or preemption is disabled.
>
> The functions to toggle the PMU and to program the PMU counters access the
> registers directly and don't access data modified by the interrupt handler.
> That, and the fact that they're always called from non-preemptible
> contexts, means that we don't need to disable interrupts or use a spinlock.
Maybe we should add a lockdep assertion that the code isn't preemptible?
I.e. add a cant_sleep() call? Or is it more that we don't need locking
because we're just doing register accesses and don't need to protect
those accesses from each other?
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