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Message-ID: <e4831ec7-dfe7-ce4d-585f-bf11a1cb1baa@gmail.com>
Date: Wed, 17 Jun 2020 14:50:35 -0700
From: Florian Fainelli <f.fainelli@...il.com>
To: Álvaro Fernández Rojas <noltari@...il.com>,
bhelgaas@...gle.com, robh+dt@...nel.org, tsbogend@...ha.franken.de,
lorenzo.pieralisi@....com, p.zabel@...gutronix.de,
jiaxun.yang@...goat.com, paulburton@...nel.org, info@...ux.net,
allison@...utok.net, kstewart@...uxfoundation.org,
tglx@...utronix.de, jonas.gorski@...il.com,
bcm-kernel-feedback-list@...adcom.com, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-mips@...r.kernel.org
Subject: Re: [PATCH 2/3] dt-bindings: Document BCM6328 PCIe Host Controller
On 6/17/2020 3:25 AM, Álvaro Fernández Rojas wrote:
> BCM6328 PCIe host controller is found on BCM6328, BCM6362 and BCM63268 SoCs.
>
> Signed-off-by: Álvaro Fernández Rojas <noltari@...il.com>
> ---
> .../bindings/pci/brcm,bcm6328-pcie.yaml | 109 ++++++++++++++++++
> 1 file changed, 109 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/brcm,bcm6328-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/brcm,bcm6328-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,bcm6328-pcie.yaml
> new file mode 100644
> index 000000000000..d2bd4933a5fa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/brcm,bcm6328-pcie.yaml
> @@ -0,0 +1,109 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/brcm,bcm6328-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: BCM6328 PCIe Host Controller Device Tree Bindings
> +
> +maintainers:
> + - Álvaro Fernández Rojas <noltari@...il.com>
> +
> +allOf:
> + - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - brcm,bcm6328-pcie
> + - brcm,bcm6362-pcie
> + - brcm,bcm63268-pcie
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: pcie
> +
> + "#interrupt-cells":
> + const: 1
> +
> + interrupt-map-mask:
> + maxItems: 1
> +
> + interrupt-map:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + ranges:
> + maxItems: 1
> +
> + reg:
> + maxItems: 1
> +
> + resets:
> + maxItems: 4
> +
> + reset-names:
> + items:
> + - const: pcie
> + - const: pcie-core
> + - const: pcie-ext
> + - const: pcie-hard
> +
> +required:
> + - brcm,serdes
> + - clocks
> + - clock-names
> + - "#interrupt-cells"
> + - interrupt-map-mask
> + - interrupt-map
> + - ranges
> + - reg
> + - resets
> + - reset-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + serdes_cntl: syscon@...01800 {
> + compatible = "syscon";
> + reg = <0x10001800 0x4>;
> + native-endian;
> + };
I believe you could be modelling the SerDes as generic PHY driver which
would be a little cleaner than the syscon approach. In newer chips like
6318 it looks like you should be able to use pcie-brcmstb.c since the
controller appears to be nearly the same and the PHY abstraction would
work nicely there.
--
Florian
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