linux-kernel - Re: [PATCH v4 3/7] iommu/mediatek: Set MISC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <aaf422f5-2ac8-252d-a064-0c1246e09acc@gmail.com>
Date:   Wed, 17 Jun 2020 11:34:55 +0200
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     Chao Hao <chao.hao@...iatek.com>, Joerg Roedel <joro@...tes.org>,
        Rob Herring <robh+dt@...nel.org>
Cc:     iommu@...ts.linux-foundation.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, wsd_upstream@...iatek.com,
        Yong Wu <yong.wu@...iatek.com>, FY Yang <fy.yang@...iatek.com>
Subject: Re: [PATCH v4 3/7] iommu/mediatek: Set MISC_CTRL register



On 17/06/2020 05:00, Chao Hao wrote:
> Add F_MMU_IN_ORDER_WR_EN definition in MISC_CTRL.
> In order to improve performance, we always disable STANDARD_AXI_MODE
> and IN_ORDER_WR_EN in MISC_CTRL.
> 
> Change since v3:

The changelog should go below the '---' as we don't want this in the git history
once the patch get's accepted.

> 1. Rename Disable STANDARD_AXI_MODE in MISC_CTRL to Set MISC_CTRL register
> 2. Add F_MMU_IN_DRDER_WR_EN definition in MISC_CTRL
>        We need to disable in_order_write to improve performance
> 
> Cc: Yong Wu <yong.wu@...iatek.com>
> Signed-off-by: Chao Hao <chao.hao@...iatek.com>
> ---
>  drivers/iommu/mtk_iommu.c | 11 +++++++++++
>  drivers/iommu/mtk_iommu.h |  1 +
>  2 files changed, 12 insertions(+)
> 
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 88d3df5b91c2..239d2cdbbc9f 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -42,6 +42,9 @@
>  #define F_INVLD_EN1				BIT(1)
>  
>  #define REG_MMU_MISC_CTRL			0x048
> +#define F_MMU_IN_ORDER_WR_EN			(BIT(1) | BIT(17))
> +#define F_MMU_STANDARD_AXI_MODE_BIT		(BIT(3) | BIT(19))
> +
>  #define REG_MMU_DCM_DIS				0x050
>  
>  #define REG_MMU_CTRL_REG			0x110
> @@ -578,6 +581,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
>  		writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
>  	}
>  
> +	if (data->plat_data->has_misc_ctrl) {

That's confusing. We renamed the register to misc_ctrl, but it's present in all
SoCs. We should find a better name for this flag to describe what the hardware
supports.

Regards,
Matthias

> +		/* For mm_iommu, it can improve performance by the setting */
> +		regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
> +		regval &= ~F_MMU_STANDARD_AXI_MODE_BIT;
> +		regval &= ~F_MMU_IN_ORDER_WR_EN;
> +		writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
> +	}
> +
>  	if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
>  			     dev_name(data->dev), (void *)data)) {
>  		writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 1b6ea839b92c..d711ac630037 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -40,6 +40,7 @@ struct mtk_iommu_plat_data {
>  
>  	/* HW will use the EMI clock if there isn't the "bclk". */
>  	bool                has_bclk;
> +	bool		    has_misc_ctrl;
>  	bool                has_vld_pa_rng;
>  	bool                reset_axi;
>  	unsigned char       larbid_remap[MTK_LARB_NR_MAX];
>