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Message-Id: <20200617105042.3824116-9-noltari@gmail.com>
Date: Wed, 17 Jun 2020 12:50:40 +0200
From: Álvaro Fernández Rojas
<noltari@...il.com>
To: p.zabel@...gutronix.de, robh+dt@...nel.org,
tsbogend@...ha.franken.de, f.fainelli@...il.com,
jonas.gorski@...il.com, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-mips@...r.kernel.org,
bcm-kernel-feedback-list@...adcom.com
Cc: Álvaro Fernández Rojas
<noltari@...il.com>
Subject: [PATCH v7 8/9] mips: bmips: dts: add BCM63268 reset controller support
BCM63268 SoCs have a reset controller for certain components.
Signed-off-by: Álvaro Fernández Rojas <noltari@...il.com>
Acked-by: Florian Fainelli <f.fainelli@...il.com>
---
v7: no changes.
v6: no changes.
v5: no changes.
v4: no changes.
v3: add new path with BCM63268 reset controller support.
arch/mips/boot/dts/brcm/bcm63268.dtsi | 6 +++++
include/dt-bindings/reset/bcm63268-reset.h | 26 ++++++++++++++++++++++
2 files changed, 32 insertions(+)
create mode 100644 include/dt-bindings/reset/bcm63268-reset.h
diff --git a/arch/mips/boot/dts/brcm/bcm63268.dtsi b/arch/mips/boot/dts/brcm/bcm63268.dtsi
index beec24145af7..0150da7e3905 100644
--- a/arch/mips/boot/dts/brcm/bcm63268.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm63268.dtsi
@@ -70,6 +70,12 @@ reboot: syscon-reboot@...00008 {
mask = <0x1>;
};
+ periph_rst: reset-controller@...00010 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x10000010 0x4>;
+ #reset-cells = <1>;
+ };
+
periph_intc: interrupt-controller@...00020 {
compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x20>,
diff --git a/include/dt-bindings/reset/bcm63268-reset.h b/include/dt-bindings/reset/bcm63268-reset.h
new file mode 100644
index 000000000000..6a6403a4c2d5
--- /dev/null
+++ b/include/dt-bindings/reset/bcm63268-reset.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM63268_H
+#define __DT_BINDINGS_RESET_BCM63268_H
+
+#define BCM63268_RST_SPI 0
+#define BCM63268_RST_IPSEC 1
+#define BCM63268_RST_EPHY 2
+#define BCM63268_RST_SAR 3
+#define BCM63268_RST_ENETSW 4
+#define BCM63268_RST_USBS 5
+#define BCM63268_RST_USBH 6
+#define BCM63268_RST_PCM 7
+#define BCM63268_RST_PCIE_CORE 8
+#define BCM63268_RST_PCIE 9
+#define BCM63268_RST_PCIE_EXT 10
+#define BCM63268_RST_WLAN_SHIM 11
+#define BCM63268_RST_DDR_PHY 12
+#define BCM63268_RST_FAP0 13
+#define BCM63268_RST_WLAN_UBUS 14
+#define BCM63268_RST_DECT 15
+#define BCM63268_RST_FAP1 16
+#define BCM63268_RST_PCIE_HARD 17
+#define BCM63268_RST_GPHY 18
+
+#endif /* __DT_BINDINGS_RESET_BCM63268_H */
--
2.27.0
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