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Message-ID: <202006180040.TJEMicB6%lkp@intel.com>
Date: Thu, 18 Jun 2020 00:40:44 +0800
From: kernel test robot <lkp@...el.com>
To: Dmytro Laktyushkin <Dmytro.Laktyushkin@....com>
Cc: kbuild-all@...ts.01.org, linux-kernel@...r.kernel.org,
Alex Deucher <alexander.deucher@....com>,
Eric Yang <eric.yang2@....com>
Subject: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1389:63:
warning: comparison of unsigned expression >= 0 is always true
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 69119673bd50b176ded34032fadd41530fb5af21
commit: 6eb3f7da3c332f23d4591063711b2a895ec2ab0f drm/amd/display: fix rn soc bb update
date: 7 weeks ago
config: i386-randconfig-s001-20200617 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-13) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.2-rc1-6-g78f577f8-dirty
git checkout 6eb3f7da3c332f23d4591063711b2a895ec2ab0f
# save the attached .config to linux build tree
make W=1 C=1 ARCH=i386 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>, old ones prefixed by <<):
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_1_0_sh_mask.h:13989:111: warning: initialized field overwritten [-Woverride-init]
13989 | #define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.h:38:16: note: in expansion of macro 'CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK'
38 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:206:2: note: in expansion of macro 'TF_SF'
206 | TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh)
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:548:2: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20_UPDATED'
548 | TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh), | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:666:3: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20'
666 | TF_REG_LIST_SH_MASK_DCN20(_MASK),
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_1_0_sh_mask.h:13989:111: note: (near initialization for 'tf_mask.CM_SHAPER_LUT_MODE')
13989 | #define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.h:38:16: note: in expansion of macro 'CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK'
38 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:206:2: note: in expansion of macro 'TF_SF'
206 | TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh)
| ^~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp.h:548:2: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20_UPDATED'
548 | TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh), | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:666:3: note: in expansion of macro 'TF_REG_LIST_SH_MASK_DCN20'
666 | TF_REG_LIST_SH_MASK_DCN20(_MASK),
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_1_0_sh_mask.h:33815:111: warning: initialized field overwritten [-Woverride-init]
33815 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in expansion of macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT'
214 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:204:2: note: in expansion of macro 'AUX_SF'
204 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh), | ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:684:2: note: in expansion of macro 'DCN_AUX_MASK_SH_LIST'
684 | DCN_AUX_MASK_SH_LIST(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_1_0_sh_mask.h:33815:111: note: (near initialization for 'aux_shift.AUX_SW_AUTOINCREMENT_DISABLE')
33815 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in expansion of macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT'
214 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:204:2: note: in expansion of macro 'AUX_SF'
204 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh), | ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:684:2: note: in expansion of macro 'DCN_AUX_MASK_SH_LIST'
684 | DCN_AUX_MASK_SH_LIST(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_1_0_sh_mask.h:33819:111: warning: initialized field overwritten [-Woverride-init]
33819 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in expansion of macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK'
214 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:204:2: note: in expansion of macro 'AUX_SF'
204 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh), | ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:688:2: note: in expansion of macro 'DCN_AUX_MASK_SH_LIST'
688 | DCN_AUX_MASK_SH_LIST(_MASK)
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_1_0_sh_mask.h:33819:111: note: (near initialization for 'aux_mask.AUX_SW_AUTOINCREMENT_DISABLE')
33819 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in expansion of macro 'DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK'
214 | .field_name = reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:204:2: note: in expansion of macro 'AUX_SF'
204 | AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh), | ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:688:2: note: in expansion of macro 'DCN_AUX_MASK_SH_LIST'
688 | DCN_AUX_MASK_SH_LIST(_MASK)
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:777:20: warning: no previous prototype for 'dcn21_i2c_hw_create' [-Wmissing-prototypes]
777 | struct dce_i2c_hw *dcn21_i2c_hw_create(
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1078:6: warning: no previous prototype for 'dcn21_calculate_wm' [-Wmissing-prototypes]
1078 | void dcn21_calculate_wm(
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1163:6: warning: no previous prototype for 'dcn21_validate_bandwidth' [-Wmissing-prototypes]
1163 | bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1293:32: warning: no previous prototype for 'dcn21_opp_create' [-Wmissing-prototypes]
1293 | struct output_pixel_processor *dcn21_opp_create(
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1309:26: warning: no previous prototype for 'dcn21_timing_generator_create' [-Wmissing-prototypes]
1309 | struct timing_generator *dcn21_timing_generator_create(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1331:13: warning: no previous prototype for 'dcn21_mpc_create' [-Wmissing-prototypes]
1331 | struct mpc *dcn21_mpc_create(struct dc_context *ctx)
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1358:35: warning: no previous prototype for 'dcn21_dsc_create' [-Wmissing-prototypes]
1358 | struct display_stream_compressor *dcn21_dsc_create(
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c: In function 'update_bw_bounding_box':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1389:63: warning: comparison of unsigned expression >= 0 is always true [-Wtype-limits]
1389 | for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
| ^~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c: At top level:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1502:24: warning: no previous prototype for 'dcn21_stream_encoder_create' [-Wmissing-prototypes]
1502 | struct stream_encoder *dcn21_stream_encoder_create(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:70:
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:489:52: warning: initialized field overwritten [-Woverride-init]
489 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:319:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
319 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:321:19: note: in expansion of macro 'BASE_INNER'
321 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:324:15: note: in expansion of macro 'BASE'
324 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + | ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:157:2: note: in expansion of macro 'SR'
157 | SR(DCFCLK_CNTL), | ^~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:280:2: note: in expansion of macro 'HWSEQ_DCN_REG_LIST'
280 | HWSEQ_DCN_REG_LIST(), | ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1520:3: note: in expansion of macro 'HWSEQ_DCN21_REG_LIST'
1520 | HWSEQ_DCN21_REG_LIST()
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/renoir_ip_offset.h:489:52: note: (near initialization for 'hwseq_reg.DCFCLK_CNTL')
489 | #define DMU_BASE__INST0_SEG2 0x000034C0
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:319:25: note: in expansion of macro 'DMU_BASE__INST0_SEG2'
319 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
| ^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:321:19: note: in expansion of macro 'BASE_INNER'
321 | #define BASE(seg) BASE_INNER(seg)
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:324:15: note: in expansion of macro 'BASE'
324 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + | ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:157:2: note: in expansion of macro 'SR'
157 | SR(DCFCLK_CNTL), | ^~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:280:2: note: in expansion of macro 'HWSEQ_DCN_REG_LIST'
280 | HWSEQ_DCN_REG_LIST(), | ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1520:3: note: in expansion of macro 'HWSEQ_DCN21_REG_LIST'
1520 | HWSEQ_DCN21_REG_LIST()
| ^~~~~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:72:
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_1_0_sh_mask.h:43237:111: warning: initialized field overwritten [-Woverride-init]
43237 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:439:28: note: in expansion of macro 'LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT'
439 | .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:676:2: note: in expansion of macro 'HWS_SF'
676 | HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), | ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1524:3: note: in expansion of macro 'HWSEQ_DCN21_MASK_SH_LIST'
1524 | HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_1_0_sh_mask.h:43237:111: note: (near initialization for 'hwseq_shift.LVTMA_BLON')
43237 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:439:28: note: in expansion of macro 'LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT'
439 | .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:676:2: note: in expansion of macro 'HWS_SF'
676 | HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), | ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1524:3: note: in expansion of macro 'HWSEQ_DCN21_MASK_SH_LIST'
1524 | HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_1_0_sh_mask.h:43253:111: warning: initialized field overwritten [-Woverride-init]
43253 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:439:28: note: in expansion of macro 'LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT'
439 | .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:677:2: note: in expansion of macro 'HWS_SF'
677 | HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
| ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1524:3: note: in expansion of macro 'HWSEQ_DCN21_MASK_SH_LIST'
1524 | HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_1_0_sh_mask.h:43253:111: note: (near initialization for 'hwseq_shift.LVTMA_PWRSEQ_TARGET_STATE_R')
43253 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:439:28: note: in expansion of macro 'LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT'
439 | .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.h:677:2: note: in expansion of macro 'HWS_SF'
677 | HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
| ^~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c:1524:3: note: in expansion of macro 'HWSEQ_DCN21_MASK_SH_LIST'
1524 | HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dcn/dcn_2_1_0_sh_mask.h:43249:111: warning: initialized field overwritten [-Woverride-init]
43249 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L
vim +1389 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.c
1330
> 1331 struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1332 {
1333 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1334 GFP_KERNEL);
1335
1336 if (!mpc20)
1337 return NULL;
1338
1339 dcn20_mpc_construct(mpc20, ctx,
1340 &mpc_regs,
1341 &mpc_shift,
1342 &mpc_mask,
1343 6);
1344
1345 return &mpc20->base;
1346 }
1347
1348 static void read_dce_straps(
1349 struct dc_context *ctx,
1350 struct resource_straps *straps)
1351 {
1352 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1353 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1354
1355 }
1356
1357
1358 struct display_stream_compressor *dcn21_dsc_create(
1359 struct dc_context *ctx, uint32_t inst)
1360 {
1361 struct dcn20_dsc *dsc =
1362 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1363
1364 if (!dsc) {
1365 BREAK_TO_DEBUGGER();
1366 return NULL;
1367 }
1368
1369 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1370 return &dsc->base;
1371 }
1372
1373 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1374 {
1375 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1376 struct clk_limit_table *clk_table = &bw_params->clk_table;
1377 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1378 unsigned int i, j, closest_clk_lvl;
1379
1380 // Default clock levels are used for diags, which may lead to overclocking.
1381 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
1382 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1383 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1384 dcn2_1_soc.num_chans = bw_params->num_channels;
1385
1386 ASSERT(clk_table->num_entries);
1387 for (i = 0; i < clk_table->num_entries; i++) {
1388 /* loop backwards*/
> 1389 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
1390 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1391 closest_clk_lvl = j;
1392 break;
1393 }
1394 }
1395
1396 clock_limits[i].state = i;
1397 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1398 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1399 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1400 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1401
1402 clock_limits[i].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1403 clock_limits[i].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1404 clock_limits[i].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1405 clock_limits[i].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1406 clock_limits[i].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1407 clock_limits[i].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1408 clock_limits[i].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1409 }
1410 for (i = 0; i < clk_table->num_entries; i++)
1411 dcn2_1_soc.clock_limits[i] = clock_limits[i];
1412 if (clk_table->num_entries) {
1413 dcn2_1_soc.num_states = clk_table->num_entries;
1414 /* duplicate last level */
1415 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1416 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
1417 }
1418 }
1419
1420 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1421 }
1422
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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