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Message-ID: <1592476935.32278.2.camel@mtkswgap22>
Date: Thu, 18 Jun 2020 18:42:15 +0800
From: Macpaul Lin <macpaul.lin@...iatek.com>
To: Stephen Boyd <sboyd@...nel.org>
CC: Michael Turquette <mturquette@...libre.com>,
<linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>,
Owen Chen <owen.chen@...iatek.com>,
Mars Cheng <mars.cheng@...iatek.com>,
"kbuild test robot" <lkp@...el.com>
Subject: Re: [PATCH] clk: mediatek: Remove ifr{0,1}_cfg_regs structures
On Tue, 2020-06-09 at 14:18 -0700, Stephen Boyd wrote:
> These aren't used and the macros that reference them aren't used either.
> Remove the dead code to avoid compile warnings.
>
> Cc: Owen Chen <owen.chen@...iatek.com>
> Cc: Mars Cheng <mars.cheng@...iatek.com>
> Cc: Macpaul Lin <macpaul.lin@...iatek.com>
> Fixes: 1aca9939bf72 ("clk: mediatek: Add MT6765 clock support")
> Reported-by: kbuild test robot <lkp@...el.com>
> Signed-off-by: Stephen Boyd <sboyd@...nel.org>
> ---
> drivers/clk/mediatek/clk-mt6765.c | 30 ------------------------------
> 1 file changed, 30 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c
> index 3ec53cb62ece..db8db1b3b79d 100644
> --- a/drivers/clk/mediatek/clk-mt6765.c
> +++ b/drivers/clk/mediatek/clk-mt6765.c
> @@ -534,18 +534,6 @@ static const struct mtk_gate top_clks[] = {
> GATE_TOP2(CLK_TOP_APLL12_DIV3, "apll12_div3", "aud_1_ck", 5),
> };
>
> -static const struct mtk_gate_regs ifr0_cg_regs = {
> - .set_ofs = 0x200,
> - .clr_ofs = 0x200,
> - .sta_ofs = 0x200,
> -};
> -
> -static const struct mtk_gate_regs ifr1_cg_regs = {
> - .set_ofs = 0x74,
> - .clr_ofs = 0x74,
> - .sta_ofs = 0x74,
> -};
> -
> static const struct mtk_gate_regs ifr2_cg_regs = {
> .set_ofs = 0x80,
> .clr_ofs = 0x84,
> @@ -570,24 +558,6 @@ static const struct mtk_gate_regs ifr5_cg_regs = {
> .sta_ofs = 0xc8,
> };
>
> -#define GATE_IFR0(_id, _name, _parent, _shift) { \
> - .id = _id, \
> - .name = _name, \
> - .parent_name = _parent, \
> - .regs = &ifr0_cg_regs, \
> - .shift = _shift, \
> - .ops = &mtk_clk_gate_ops_no_setclr_inv, \
> - }
> -
> -#define GATE_IFR1(_id, _name, _parent, _shift) { \
> - .id = _id, \
> - .name = _name, \
> - .parent_name = _parent, \
> - .regs = &ifr1_cg_regs, \
> - .shift = _shift, \
> - .ops = &mtk_clk_gate_ops_no_setclr, \
> - }
> -
> #define GATE_IFR2(_id, _name, _parent, _shift) { \
> .id = _id, \
> .name = _name, \
Thank you so much!
Owen and I were busy in other issues hence cannot help fix this issue
in time.
Thanks a lot!
BR,
Macpaul Lin
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