linux-kernel - Re: [PATCH v4 7/7] iommu/mediatek: Add mt6779 basic support

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Message-ID: <9618cc95-99ac-63d0-f502-335e38819842@gmail.com>
Date:   Thu, 18 Jun 2020 18:00:05 +0200
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     chao hao <Chao.Hao@...iatek.com>
Cc:     Joerg Roedel <joro@...tes.org>, Rob Herring <robh+dt@...nel.org>,
        iommu@...ts.linux-foundation.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, wsd_upstream@...iatek.com,
        Yong Wu <yong.wu@...iatek.com>, FY Yang <fy.yang@...iatek.com>
Subject: Re: [PATCH v4 7/7] iommu/mediatek: Add mt6779 basic support



On 18/06/2020 13:54, chao hao wrote:
> On Wed, 2020-06-17 at 11:33 +0200, Matthias Brugger wrote:
>>
>> On 17/06/2020 05:00, Chao Hao wrote:
>>> 1. Start from mt6779, INVLDT_SEL move to offset=0x2c, so we add
>>>    REG_MMU_INV_SEL_GEN2 definition and mt6779 uses it.
>>> 2. Change PROTECT_PA_ALIGN from 128 byte to 256 byte.
>>> 3. For REG_MMU_CTRL_REG register, we only need to change bit[2:0],
>>>    others bits keep default value, ex: enable victim tlb.
>>> 4. Add mt6779_data to support mm_iommu HW init.
>>>
>>> Change since v3:
>>> 1. When setting MMU_CTRL_REG, we don't need to include mt8173.
>>>
>>> Cc: Yong Wu <yong.wu@...iatek.com>
>>> Signed-off-by: Chao Hao <chao.hao@...iatek.com>
>>> ---
>>>  drivers/iommu/mtk_iommu.c | 20 ++++++++++++++++++--
>>>  drivers/iommu/mtk_iommu.h |  1 +
>>>  2 files changed, 19 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
>>> index c706bca6487e..def2e996683f 100644
>>> --- a/drivers/iommu/mtk_iommu.c
>>> +++ b/drivers/iommu/mtk_iommu.c
>>> @@ -37,6 +37,11 @@
>>>  #define REG_MMU_INVLD_START_A			0x024
>>>  #define REG_MMU_INVLD_END_A			0x028
>>>  
>>> +/* In latest Coda, MMU_INV_SEL's offset is changed to 0x02c.
>>> + * So we named offset = 0x02c to "REG_MMU_INV_SEL_GEN2"
>>> + * and offset = 0x038 to "REG_MMU_INV_SEL_GEN1".
>>> + */
>>
>> Please delete the comment, this should be understandable from the git history
> 
> ok, thanks
> 
>>
>>> +#define REG_MMU_INV_SEL_GEN2			0x02c
>>>  #define REG_MMU_INV_SEL_GEN1			0x038
>>>  #define F_INVLD_EN0				BIT(0)
>>>  #define F_INVLD_EN1				BIT(1)
>>> @@ -98,7 +103,7 @@
>>>  #define F_MMU_INT_ID_LARB_ID(a)			(((a) >> 7) & 0x7)
>>>  #define F_MMU_INT_ID_PORT_ID(a)			(((a) >> 2) & 0x1f)
>>>  
>>> -#define MTK_PROTECT_PA_ALIGN			128
>>> +#define MTK_PROTECT_PA_ALIGN			256
>>
>> Do we need 512 bytes for all gen2 IOMMUs?
>> I'm not sure if we should add this in plat_data or if we should just bump up the
>> value for all SoCs.
>> In both cases this should be a separate patch.
>>
> From mt6779, MTK_PROTECT_PA_ALIGN is extend to 256 bytes and don't be
> changed for a long time from our HW designer comment. The legacy iommu
> also can use it, mabye it doesn't set it by platform.
> 

Ok then just bump it to 256 in a new patch. Thanks for clarification.

> 
>>>  
>>>  /*
>>>   * Get the local arbiter ID and the portid within the larb arbiter
>>> @@ -543,11 +548,12 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
>>>  		return ret;
>>>  	}
>>>  
>>> +	regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);
>>>  	if (data->plat_data->m4u_plat == M4U_MT8173)
>>>  		regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
>>>  			 F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
>>>  	else
>>> -		regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR;
>>> +		regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
>>
>> Why do we change this, is it that the bootloader for mt6779 set some values in
>> the register we have to keep? In this case I think we should update the regval
>> accordingly.
> 
> For REG_MMU_CTRL_REG, bit[12] represents victim_tlb_en feature and
> victim_tlb is enable defaultly(bit[12]=1),but if we use "regval =
> F_MMU_TF_PROT_TO_PROGRAM_ADDR", victim_tlb will disable, it will drop
> iommu performace for mt6779
> 

Got it. Please put that in a separate patch then.

Regards,
Matthias

> 
>>
>>>  	writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
>>>  
>>>  	regval = F_L2_MULIT_HIT_EN |
>>> @@ -797,6 +803,15 @@ static const struct mtk_iommu_plat_data mt2712_data = {
>>>  	.larbid_remap   = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
>>>  };
>>>  
>>> +static const struct mtk_iommu_plat_data mt6779_data = {
>>> +	.m4u_plat      = M4U_MT6779,
>>> +	.has_sub_comm  = true,
>>> +	.has_wr_len    = true,
>>> +	.has_misc_ctrl = true,
>>> +	.inv_sel_reg   = REG_MMU_INV_SEL_GEN2,
>>> +	.larbid_remap  = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
>>> +};
>>> +
>>>  static const struct mtk_iommu_plat_data mt8173_data = {
>>>  	.m4u_plat     = M4U_MT8173,
>>>  	.has_4gb_mode = true,
>>> @@ -815,6 +830,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
>>>  
>>>  static const struct of_device_id mtk_iommu_of_ids[] = {
>>>  	{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
>>> +	{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
>>>  	{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
>>>  	{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
>>>  	{}
>>> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
>>> index 9971cedd72ea..fb79e710c8d9 100644
>>> --- a/drivers/iommu/mtk_iommu.h
>>> +++ b/drivers/iommu/mtk_iommu.h
>>> @@ -31,6 +31,7 @@ struct mtk_iommu_suspend_reg {
>>>  enum mtk_iommu_plat {
>>>  	M4U_MT2701,
>>>  	M4U_MT2712,
>>> +	M4U_MT6779,
>>>  	M4U_MT8173,
>>>  	M4U_MT8183,
>>>  };
>>>
>