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Message-ID: <1592497015.10773.21.camel@mtkswgap22>
Date: Fri, 19 Jun 2020 00:16:55 +0800
From: Hanks Chen <hanks.chen@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>
CC: Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
"Stephen Boyd" <sboyd@...nel.org>,
Sean Wang <sean.wang@...nel.org>,
mtk01761 <wendell.lin@...iatek.com>,
Andy Teng <andy.teng@...iatek.com>,
<linux-gpio@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<wsd_upstream@...iatek.com>, CC Hwang <cc.hwang@...iatek.com>,
Loda Chou <loda.chou@...iatek.com>
Subject: Re: [PATCH v6 6/7] clk: mediatek: add UART0 clock support
On Thu, 2020-06-18 at 17:51 +0200, Matthias Brugger wrote:
>
> On 18/06/2020 13:33, Hanks Chen wrote:
> > Add MT6779 UART0 clock support.
> >
>
> Please a dd fixes tag:
>
> Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
Got it, I'll add it in next version.
>
> > Signed-off-by: Hanks Chen <hanks.chen@...iatek.com>
> > Signed-off-by: mtk01761 <wendell.lin@...iatek.com>
>
> Must be a real name not "mtk01761"
Oops, I'll update his name.
Thank you for your comment.
>
> > ---
> > drivers/clk/mediatek/clk-mt6779.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
> > index 9766ccc..6e0d3a1 100644
> > --- a/drivers/clk/mediatek/clk-mt6779.c
> > +++ b/drivers/clk/mediatek/clk-mt6779.c
> > @@ -919,6 +919,8 @@
> > "pwm_sel", 19),
> > GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
> > "pwm_sel", 21),
> > + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
> > + "uart_sel", 22),
> > GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
> > "uart_sel", 23),
> > GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
> >
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