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Message-Id: <20200618222614.14061-2-tanmay@codeaurora.org>
Date: Thu, 18 Jun 2020 15:26:09 -0700
From: Tanmay Shah <tanmay@...eaurora.org>
To: robh+dt@...nel.org, swboyd@...omium.org, sam@...nborg.org
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, seanpaul@...omium.org,
robdclark@...il.com, daniel@...ll.ch, airlied@...ux.ie,
aravindh@...eaurora.org, abhinavk@...eaurora.org,
chandanu@...eaurora.org, varar@...eaurora.org,
Tanmay Shah <tanmay@...eaurora.org>
Subject: [PATCH v7 1/6] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon
From: Chandan Uddaraju <chandanu@...eaurora.org>
Add bindings for Snapdragon DisplayPort controller driver.
Changes in V2:
Provide details about sel-gpio
Changes in V4:
Provide details about max dp lanes
Change the commit text
Changes in V5:
moved dp.txt to yaml file
Changes in v6:
- Squash all AUX LUT properties into one pattern Property
- Make aux-cfg[0-9]-settings properties optional
- Remove PLL/PHY bindings from DP controller dts
- Add DP clocks description
- Remove _clk suffix from clock names
- Rename pixel clock to stream_pixel
- Remove redundant bindings (GPIO, PHY, HDCP clock, etc..)
- Fix indentation
- Add Display Port as interface of DPU in DPU bindings
and add port mapping accordingly.
Chages in v7:
- Add dp-controller.yaml file common between multiple SOC
- Rename dp-sc7180.yaml to dp-controller-sc7180.yaml
- change compatible string and add SOC name to it.
- Remove Root clock generator for pixel clock
- Add assigned-clocks and assigned-clock-parents bindings
- Remove redundant properties, descriptions and blank lines
- Add DP port in DPU bindings
- Update depends-on tag in commit message and rebase change accordingly
This change depends-on:
- https://patchwork.freedesktop.org/patch/366159/
Signed-off-by: Chandan Uddaraju <chandanu@...eaurora.org>
Signed-off-by: Vara Reddy <varar@...eaurora.org>
Signed-off-by: Tanmay Shah <tanmay@...eaurora.org>
---
.../display/msm/dp-controller-sc7180.yaml | 147 ++++++++++++++++++
.../bindings/display/msm/dp-controller.yaml | 59 +++++++
.../bindings/display/msm/dpu-sc7180.yaml | 11 ++
3 files changed, 217 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml
create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml
new file mode 100644
index 000000000000..8dd56816dbbd
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dp-controller-sc7180.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MSM SC7180 Display Port Controller.
+
+maintainers:
+ - Chandan Uddaraju <chandanu@...eaurora.org>
+ - Vara Reddy <varar@...eaurora.org>
+ - Tanmay Shah <tanmay@...eaurora.org>
+
+description: |
+ Device tree bindings for DP host controller for MSM SC7180 target
+ that are compatible with VESA Display Port interface specification.
+
+allOf:
+ - $ref: dp-controller.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,sc7180-dp
+
+ reg:
+ maxItems: 1
+ reg-names:
+ const: dp_controller
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 4
+ items:
+ - description: Display Port AUX clock
+ - description: Display Port Link clock
+ - description: Link interface clock between DP and PHY
+ - description: Display Port Pixel clock
+
+ clock-names:
+ items:
+ - const: core_aux
+ - const: ctrl_link
+ - const: ctrl_link_iface
+ - const: stream_pixel
+
+ "#clock-cells":
+ const: 1
+
+ assigned-clocks:
+ maxItems: 1
+ assigned-clock-parents:
+ maxItems: 1
+
+ data-lanes:
+ $ref: "/schemas/types.yaml#/definitions/uint32-array"
+ minItems: 1
+ maxItems: 4
+
+ vdda-1p2-supply:
+ description: phandle to vdda 1.2V regulator node.
+
+ vdda-0p9-supply:
+ description: phandle to vdda 0.9V regulator node.
+
+ ports:
+ type: object
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ port@0:
+ type: object
+ port@1:
+ type: object
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-parents
+ - vdda-1p2-supply
+ - vdda-0p9-supply
+ - data-lanes
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ msm_dp: displayport-controller@...0000{
+ compatible = "qcom,sc7180-dp";
+ reg = <0 0xae90000 0 0x1400>;
+ reg-names = "dp_controller";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <12 0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ clock-names = "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ #clock-cells = <1>;
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <&dp_phy 1>;
+
+ vdda-1p2-supply = <&vreg_l3c_1p2>;
+ vdda-0p9-supply = <&vreg_l4a_0p8>;
+
+ data-lanes = <0 1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_out: endpoint {
+ };
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
new file mode 100644
index 000000000000..7f3bc0878d8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Port Controller.
+
+maintainers:
+ - Chandan Uddaraju <chandanu@...eaurora.org>
+ - Vara Reddy <varar@...eaurora.org>
+ - Tanmay Shah <tanmay@...eaurora.org>
+
+description: |
+ Device tree bindings for MSM Display Port which supports DP host controllers
+ that are compatible with VESA Display Port interface specification.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,sc7180-dp
+
+ reg:
+ maxItems: 1
+ reg-names:
+ const: dp_controller
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 4
+ items:
+ - description: Display Port AUX clock
+ - description: Display Port Link clock
+ - description: Link interface clock between DP and PHY
+ - description: Display Port Pixel clock
+
+ clock-names:
+ items:
+ - const: core_aux
+ - const: ctrl_link
+ - const: ctrl_link_iface
+ - const: stream_pixel
+
+ assigned-clocks:
+ maxItems: 1
+ assigned-clock-parents:
+ maxItems: 1
+
+ data-lanes:
+ $ref: "/schemas/types.yaml#/definitions/uint32-array"
+ minItems: 1
+ maxItems: 4
+
+ ports:
+ type: object
+...
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
index b5607f9429d5..9be71558c517 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
@@ -141,6 +141,9 @@ patternProperties:
port@1:
type: object
description: DPU_INTF2 (DSI2)
+ port@2:
+ type: object
+ description: DPU_INTF0 (DP)
assigned-clocks:
description: |
@@ -237,6 +240,14 @@ examples:
remote-endpoint = <&dsi0_in>;
};
};
+
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&dp_in>;
+ };
+ };
+
};
};
};
--
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