linux-kernel - Re: [PATCH 08/21] x86/msr-index: Add bunch of MSRs for Arch LBR

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Message-ID: <20200619191150.GH576888@hirez.programming.kicks-ass.net>
Date:   Fri, 19 Jun 2020 21:11:50 +0200
From:   Peter Zijlstra <peterz@...radead.org>
To:     kan.liang@...ux.intel.com
Cc:     mingo@...hat.com, acme@...nel.org, tglx@...utronix.de,
        bp@...en8.de, x86@...nel.org, linux-kernel@...r.kernel.org,
        mark.rutland@....com, alexander.shishkin@...ux.intel.com,
        jolsa@...hat.com, namhyung@...nel.org, dave.hansen@...el.com,
        yu-cheng.yu@...el.com, bigeasy@...utronix.de, gorcunov@...il.com,
        hpa@...or.com, alexey.budankov@...ux.intel.com, eranian@...gle.com,
        ak@...ux.intel.com, like.xu@...ux.intel.com,
        yao.jin@...ux.intel.com
Subject: Re: [PATCH 08/21] x86/msr-index: Add bunch of MSRs for Arch LBR

On Fri, Jun 19, 2020 at 07:03:56AM -0700, kan.liang@...ux.intel.com wrote:

> +#define ARCH_LBR_INFO_MISPRED		BIT_ULL(63)
> +#define ARCH_LBR_INFO_IN_TSX		BIT_ULL(62)
> +#define ARCH_LBR_INFO_TSX_ABORT		BIT_ULL(61)

That's identical to what we already have.

> +#define ARCH_LBR_INFO_CYC_CNT_VALID	BIT_ULL(60)

If you call that LBR_INFO_CYC_VALID or something, then we good there.

> +#define ARCH_LBR_INFO_BR_TYPE_OFFSET	56
> +#define ARCH_LBR_INFO_BR_TYPE		(0xfull << ARCH_LBR_INFO_BR_TYPE_OFFSET)

Same

> +#define ARCH_LBR_INFO_CYC_CNT		0xffff

And we already have that in LBR_INFO_CYCLES.