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Date: Sat, 20 Jun 2020 04:41:36 +0800
From: kernel test robot <lkp@...el.com>
To: Eric Yang <Eric.Yang2@....com>
Cc: kbuild-all@...ts.01.org, linux-kernel@...r.kernel.org,
Alex Deucher <alexander.deucher@....com>,
Sung Lee <sung.lee@....com>, Tony Cheng <Tony.Cheng@....com>
Subject: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3262:1:
warning: the frame size of 1160 bytes is larger than 1024 bytes
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 5e857ce6eae7ca21b2055cca4885545e29228fe2
commit: a39a58166901f7e72088c5eedbd17e481f0722ea drm/amd/display: fix inputting clk lvl into dml for RN
date: 4 months ago
config: i386-randconfig-r024-20200619 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-13) 9.3.0
reproduce (this is a W=1 build):
git checkout a39a58166901f7e72088c5eedbd17e481f0722ea
# save the attached .config to linux build tree
make W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>, old ones prefixed by <<):
1239 | HWSEQ_DCN2_REG_LIST()
| ^~~~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:82:
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_dmcu.h:283:23: warning: 'abm_gain_stepsize' defined but not used [-Wunused-const-variable=]
283 | static const uint32_t abm_gain_stepsize = 0x0060;
| ^~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:65:
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:133:29: warning: 'VCN_BASE' defined but not used [-Wunused-const-variable=]
133 | static const struct IP_BASE VCN_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:127:29: warning: 'UMC_BASE' defined but not used [-Wunused-const-variable=]
127 | static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0, 0, 0, 0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:121:29: warning: 'THM_BASE' defined but not used [-Wunused-const-variable=]
121 | static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:115:29: warning: 'SMUIO_BASE' defined but not used [-Wunused-const-variable=]
115 | static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:109:29: warning: 'RSMU_BASE' defined but not used [-Wunused-const-variable=]
109 | static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:103:29: warning: 'OSSSYS_BASE' defined but not used [-Wunused-const-variable=]
103 | static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } },
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:97:29: warning: 'NBIO_BASE' defined but not used [-Wunused-const-variable=]
97 | static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:91:29: warning: 'MP1_BASE' defined but not used [-Wunused-const-variable=]
91 | static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:85:29: warning: 'MP0_BASE' defined but not used [-Wunused-const-variable=]
85 | static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:79:29: warning: 'MMHUB_BASE' defined but not used [-Wunused-const-variable=]
79 | static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } },
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:73:29: warning: 'HDP_BASE' defined but not used [-Wunused-const-variable=]
73 | static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:67:29: warning: 'GC_BASE' defined but not used [-Wunused-const-variable=]
67 | static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0, 0, 0, 0 } },
| ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:61:29: warning: 'FUSE_BASE' defined but not used [-Wunused-const-variable=]
61 | static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0, 0 } },
| ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:55:29: warning: 'DCN_BASE' defined but not used [-Wunused-const-variable=]
55 | static const struct IP_BASE DCN_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0, 0 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:49:29: warning: 'DF_BASE' defined but not used [-Wunused-const-variable=]
49 | static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0, 0 } },
| ^~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:65:
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:43:29: warning: 'CLK_BASE' defined but not used [-Wunused-const-variable=]
43 | static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x00017E00, 0x0001B000 } },
| ^~~~~~~~
drivers/gpu/drm/amd/amdgpu/../include/navi10_ip_offset.h:37:29: warning: 'ATHUB_BASE' defined but not used [-Wunused-const-variable=]
37 | static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0, 0 } },
| ^~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/inc/core_types.h:85,
from drivers/gpu/drm/amd/amdgpu/../display/dc/inc/resource.h:28,
from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:34:
drivers/gpu/drm/amd/amdgpu/../display/dc/inc/hw/dpp.h:50:42: warning: 'dpp_input_csc_matrix' defined but not used [-Wunused-const-variable=]
50 | static const struct dpp_input_csc_matrix dpp_input_csc_matrix[] = {
| ^~~~~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/inc/core_types.h:32,
from drivers/gpu/drm/amd/amdgpu/../display/dc/inc/resource.h:28,
from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:34:
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:124:22: warning: 'DP_DVI_CONVERTER_ID_4' defined but not used [-Wunused-const-variable=]
124 | static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
| ^~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:122:22: warning: 'DP_VGA_LVDS_CONVERTER_ID_3' defined but not used [-Wunused-const-variable=]
122 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:120:22: warning: 'DP_VGA_LVDS_CONVERTER_ID_2' defined but not used [-Wunused-const-variable=]
120 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:33,
from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30,
from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services.h:37,
from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:29:
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:76:32: warning: 'dc_fixpt_ln2_div_2' defined but not used [-Wunused-const-variable=]
76 | static const struct fixed31_32 dc_fixpt_ln2_div_2 = { 1488522236LL };
| ^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:75:32: warning: 'dc_fixpt_ln2' defined but not used [-Wunused-const-variable=]
75 | static const struct fixed31_32 dc_fixpt_ln2 = { 2977044471LL };
| ^~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:74:32: warning: 'dc_fixpt_e' defined but not used [-Wunused-const-variable=]
74 | static const struct fixed31_32 dc_fixpt_e = { 11674931555LL };
| ^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:73:32: warning: 'dc_fixpt_two_pi' defined but not used [-Wunused-const-variable=]
73 | static const struct fixed31_32 dc_fixpt_two_pi = { 26986075409LL };
| ^~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:72:32: warning: 'dc_fixpt_pi' defined but not used [-Wunused-const-variable=]
72 | static const struct fixed31_32 dc_fixpt_pi = { 13493037705LL };
| ^~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:67:32: warning: 'dc_fixpt_zero' defined but not used [-Wunused-const-variable=]
67 | static const struct fixed31_32 dc_fixpt_zero = { 0 };
| ^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c: In function 'dcn20_update_bounding_box':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3262:1: warning: the frame size of 1160 bytes is larger than 1024 bytes [-Wframe-larger-than=]
3262 | }
| ^
vim +3262 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3201
44ce0cd3b5147d1 Dmytro Laktyushkin 2019-09-25 3202 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3203 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3204 {
960b6f4f2d2e96d Raul E Rangel 2019-10-03 3205 struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES];
f18bc4e53ad60d3 Jun Lei 2019-05-09 3206 int i;
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3207 int num_calculated_states = 0;
f18bc4e53ad60d3 Jun Lei 2019-05-09 3208 int min_dcfclk = 0;
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3209
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3210 if (num_states == 0)
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3211 return;
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3212
960b6f4f2d2e96d Raul E Rangel 2019-10-03 3213 memset(calculated_states, 0, sizeof(calculated_states));
960b6f4f2d2e96d Raul E Rangel 2019-10-03 3214
f18bc4e53ad60d3 Jun Lei 2019-05-09 3215 if (dc->bb_overrides.min_dcfclk_mhz > 0)
f18bc4e53ad60d3 Jun Lei 2019-05-09 3216 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
6ce2427db71ca69 Alvin Lee 2019-09-27 3217 else {
6ce2427db71ca69 Alvin Lee 2019-09-27 3218 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
6ce2427db71ca69 Alvin Lee 2019-09-27 3219 min_dcfclk = 310;
ff4258d59031f78 Jun Lei 2019-06-03 3220 else
ff4258d59031f78 Jun Lei 2019-06-03 3221 // Accounting for SOC/DCF relationship, we can go as high as
6ce2427db71ca69 Alvin Lee 2019-09-27 3222 // 506Mhz in Vmin.
6ce2427db71ca69 Alvin Lee 2019-09-27 3223 min_dcfclk = 506;
6ce2427db71ca69 Alvin Lee 2019-09-27 3224 }
f18bc4e53ad60d3 Jun Lei 2019-05-09 3225
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3226 for (i = 0; i < num_states; i++) {
f18bc4e53ad60d3 Jun Lei 2019-05-09 3227 int min_fclk_required_by_uclk;
f18bc4e53ad60d3 Jun Lei 2019-05-09 3228 calculated_states[i].state = i;
f18bc4e53ad60d3 Jun Lei 2019-05-09 3229 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3230
5d36f78311cfff7 Jun Lei 2019-05-22 3231 // FCLK:UCLK ratio is 1.08
5f65ae344f1493c Arnd Bergmann 2019-07-08 3232 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3233
f18bc4e53ad60d3 Jun Lei 2019-05-09 3234 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
f18bc4e53ad60d3 Jun Lei 2019-05-09 3235 min_dcfclk : min_fclk_required_by_uclk;
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3236
f18bc4e53ad60d3 Jun Lei 2019-05-09 3237 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
f18bc4e53ad60d3 Jun Lei 2019-05-09 3238 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3239
f18bc4e53ad60d3 Jun Lei 2019-05-09 3240 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
f18bc4e53ad60d3 Jun Lei 2019-05-09 3241 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3242
f18bc4e53ad60d3 Jun Lei 2019-05-09 3243 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
f18bc4e53ad60d3 Jun Lei 2019-05-09 3244 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
f18bc4e53ad60d3 Jun Lei 2019-05-09 3245 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3246
f18bc4e53ad60d3 Jun Lei 2019-05-09 3247 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3248
f18bc4e53ad60d3 Jun Lei 2019-05-09 3249 num_calculated_states++;
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3250 }
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3251
6da16270ee026a0 Jun Lei 2019-07-03 3252 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
6da16270ee026a0 Jun Lei 2019-07-03 3253 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
6da16270ee026a0 Jun Lei 2019-07-03 3254 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
6da16270ee026a0 Jun Lei 2019-07-03 3255
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3256 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3257 bb->num_states = num_calculated_states;
f18bc4e53ad60d3 Jun Lei 2019-05-09 3258
f18bc4e53ad60d3 Jun Lei 2019-05-09 3259 // Duplicate the last state, DML always an extra state identical to max state to work
f18bc4e53ad60d3 Jun Lei 2019-05-09 3260 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
f18bc4e53ad60d3 Jun Lei 2019-05-09 3261 bb->clock_limits[num_calculated_states].state = bb->num_states;
7ed4e6352c16fe0 Harry Wentland 2019-02-22 @3262 }
7ed4e6352c16fe0 Harry Wentland 2019-02-22 3263
:::::: The code at line 3262 was first introduced by commit
:::::: 7ed4e6352c16fe018864bc4e626c48e27a0cefee drm/amd/display: Add DCN2 HW Sequencer and Resource
:::::: TO: Harry Wentland <harry.wentland@....com>
:::::: CC: Alex Deucher <alexander.deucher@....com>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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