linux-kernel - Re: [PATCH v5 2/7] arm64: perf: Avoid PMXEV* indirection

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <159255518036.62212.17118495764504925359@swboyd.mtv.corp.google.com>
Date:   Fri, 19 Jun 2020 01:26:20 -0700
From:   Stephen Boyd <swboyd@...omium.org>
To:     Alexandru Elisei <alexandru.elisei@....com>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc:     mark.rutland@....com, Julien Thierry <julien.thierry@....com>,
        Peter Zijlstra <peterz@...radead.org>, maz@...nel.org,
        Jiri Olsa <jolsa@...hat.com>,
        Will Deacon <will.deacon@....com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Ingo Molnar <mingo@...hat.com>, catalin.marinas@....com,
        Namhyung Kim <namhyung@...nel.org>, will@...nel.org,
        Julien Thierry <julien.thierry.kdev@...il.com>
Subject: Re: [PATCH v5 2/7] arm64: perf: Avoid PMXEV* indirection

Quoting Alexandru Elisei (2020-06-18 03:51:08)
> On 6/17/20 9:11 PM, Stephen Boyd wrote:
> > Quoting Alexandru Elisei (2020-06-17 04:38:46)
> >> From: Mark Rutland <mark.rutland@....com>
> >> @@ -433,8 +494,9 @@ static u64 armv8pmu_read_counter(struct perf_event *event)
> >>  
> >>  static inline void armv8pmu_write_evcntr(int idx, u64 value)
> >>  {
> >> -       armv8pmu_select_counter(idx);
> >> -       write_sysreg(value, pmxevcntr_el0);
> >> +       u32 counter = ARMV8_IDX_TO_COUNTER(idx);
> > Might be a good idea to make ARMV8_IDX_TO_COUNTER a static inline
> > function that has a return type of u32. I had to go check the code to
> > make sure it wasn't something larger.
> 
> Architecturally, there are at most 32 counter registers, which would fit in an s8,
> so I don't think type checking would really help us here.

Ok. It would have saved me a few seconds while reading the code, but I
guess if I hold the architecture in my head I'll be ok too.