linux-kernel - Re: [PATCH 1/2] x86/fpu: Reset MXCSR to default in kernel_fpu

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CALCETrU0C5yVwfAOj+v1RqNBZY+phXrdvCBZMKdOXOExBgMbVg@mail.gmail.com>
Date:   Mon, 22 Jun 2020 11:33:23 -0700
From:   Andy Lutomirski <luto@...nel.org>
To:     Borislav Petkov <bp@...en8.de>
Cc:     Andy Lutomirski <luto@...nel.org>, X86 ML <x86@...nel.org>,
        jpa@...nelbug.mail.kapsi.fi, Dave Hansen <dave.hansen@...el.com>,
        LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] x86/fpu: Reset MXCSR to default in kernel_fpu_begin()

On Mon, Jun 22, 2020 at 10:09 AM Borislav Petkov <bp@...en8.de> wrote:
>
> On Fri, Jun 19, 2020 at 11:01:44AM -0700, Andy Lutomirski wrote:
> > On Fri, Jun 19, 2020 at 10:41 AM Borislav Petkov <bp@...en8.de> wrote:
> > >
> > > From: Petteri Aimonen <jpa@....mail.kapsi.fi>
> > >
> > > Previously, kernel floating point code would run with the MXCSR control
> > > register value last set by userland code by the thread that was active
> > > on the CPU core just before kernel call. This could affect calculation
> > > results if rounding mode was changed, or a crash if a FPU/SIMD exception
> > > was unmasked.
> > >
> > > Restore MXCSR to the kernel's default value.
> > >
> > >  [ bp: Carve out from a bigger patch by Petteri, add feature check, add
> > >    FNINIT call too (amluto). ]
> >
> > Acked-by: Andy Lutomirski <luto@...nel.org>
> >
> > but:
> >
> > shouldn't kernel_fpu_begin() end with a barrier()?
>
> the "fninit" thing is already asm volatile or do you want the explicit
> memory clobber of barrier?
>
> If so, why?
>
> The LDMXCSR and FNINIT have effect only on hardware state...
>

Suppose you do:

double x = 1.0;

kernel_fpu_begin();

x += 2.0;

We want to make sure that GCC puts things in the right order.  I
suppose that even a memory clobber is insufficient here, though.