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Message-ID: <20200622141737.GA30611@kernel.org>
Date: Mon, 22 Jun 2020 11:17:37 -0300
From: Arnaldo Carvalho de Melo <acme@...nel.org>
To: Borislav Petkov <bp@...en8.de>
Cc: Stephen Rothwell <sfr@...b.auug.org.au>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...e.hu>, "H. Peter Anvin" <hpa@...or.com>,
Peter Zijlstra <peterz@...radead.org>,
Linux Next Mailing List <linux-next@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Guenter Roeck <linux@...ck-us.net>
Subject: Re: [PATCH -v2] x86/msr: Move the F15h MSRs where they belong
Em Mon, Jun 22, 2020 at 03:04:07PM +0200, Borislav Petkov escreveu:
> On Mon, Jun 22, 2020 at 11:38:24AM +1000, Stephen Rothwell wrote:
> > I applied that patch to the tip tree merge today.
> >
> > Tested-by: Stephen Rothwell <sfr@...b.auug.org.au> # build tested
>
> Here's v2 instead, addressing acme's request. I didn't rebase the
> x86/cleanups branch because I'd like to have this case documented.
>
> acme, ACK?
So this reverts the change you made to the tools copy of that file and
then does the change you need to the kernel sources, ok.
In the future the change will be made just in the kernel files, as
kernel developers don't have to have the burden of checking if tooling
continues to work when they change kernel files.
That way later the perf developers get the warning in the perf build
process, see how this change in a file that is a copy from the kernel
sources affects tooling, and act upon it, simply updating the copy or
doing that + extra tooling adjustments, perhaps a new feature, etc.
Acked-by: Arnaldo Carvalho de Melo <acme@...hat.com>
- Arnaldo
> Thx.
>
> ---
> From c1c1a26bc631fafb68ed30c5164d0231acc500ee Mon Sep 17 00:00:00 2001
> From: Borislav Petkov <bp@...e.de>
> Date: Sun, 21 Jun 2020 12:41:53 +0200
>
> 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs")
>
> moved the three F15h power MSRs to the architectural list but that was
> wrong as they belong in the family 0x15 list. That also caused:
>
> In file included from trace/beauty/tracepoints/x86_msr.c:10:
> perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: error: initialized field overwritten [-Werror=override-init]
> 292 | [0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC",
> | ^~~~~~~~~~~
> perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: note: (near initialization for 'x86_AMD_V_KVM_MSRs[640]')
>
> due to MSR_F15H_PTSC ending up being defined twice. Move them where they
> belong and drop the duplicate.
>
> Also, drop the respective tools/ changes of the msr-index.h copy the
> above commit added because perf tool developers prefer to go through
> those changes themselves in order to figure out whether changes to the
> kernel headers would need additional handling in perf.
>
> Fixes: 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs")
> Reported-by: Stephen Rothwell <sfr@...b.auug.org.au>
> Signed-off-by: Borislav Petkov <bp@...e.de>
> Link: https://lkml.kernel.org/r/20200621163323.14e8533f@canb.auug.org.au
> ---
> arch/x86/include/asm/msr-index.h | 5 ++---
> tools/arch/x86/include/asm/msr-index.h | 5 +----
> 2 files changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index eb9537254920..63ed8fe35738 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -422,11 +422,8 @@
> #define MSR_AMD_PERF_CTL 0xc0010062
> #define MSR_AMD_PERF_STATUS 0xc0010063
> #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
> -#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
> -#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
> #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
> #define MSR_AMD64_OSVW_STATUS 0xc0010141
> -#define MSR_F15H_PTSC 0xc0010280
> #define MSR_AMD_PPIN_CTL 0xc00102f0
> #define MSR_AMD_PPIN 0xc00102f1
> #define MSR_AMD64_CPUID_FN_1 0xc0011004
> @@ -469,6 +466,8 @@
> #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
>
> /* Fam 15h MSRs */
> +#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
> +#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
> #define MSR_F15H_PERF_CTL 0xc0010200
> #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
> #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
> diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
> index 7dfd45bb6cdb..ef452b817f44 100644
> --- a/tools/arch/x86/include/asm/msr-index.h
> +++ b/tools/arch/x86/include/asm/msr-index.h
> @@ -414,18 +414,15 @@
> #define MSR_AMD64_PATCH_LEVEL 0x0000008b
> #define MSR_AMD64_TSC_RATIO 0xc0000104
> #define MSR_AMD64_NB_CFG 0xc001001f
> +#define MSR_AMD64_CPUID_FN_1 0xc0011004
> #define MSR_AMD64_PATCH_LOADER 0xc0010020
> #define MSR_AMD_PERF_CTL 0xc0010062
> #define MSR_AMD_PERF_STATUS 0xc0010063
> #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
> -#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
> -#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
> #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
> #define MSR_AMD64_OSVW_STATUS 0xc0010141
> -#define MSR_F15H_PTSC 0xc0010280
> #define MSR_AMD_PPIN_CTL 0xc00102f0
> #define MSR_AMD_PPIN 0xc00102f1
> -#define MSR_AMD64_CPUID_FN_1 0xc0011004
> #define MSR_AMD64_LS_CFG 0xc0011020
> #define MSR_AMD64_DC_CFG 0xc0011022
> #define MSR_AMD64_BU_CFG2 0xc001102a
> --
> 2.21.0
>
> --
> Regards/Gruss,
> Boris.
>
> https://people.kernel.org/tglx/notes-about-netiquette
--
- Arnaldo
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