linux-kernel - Re: [PATCH] ARM: exynos: clear L310_AUX_CTRL_FULL_LINE_ZERO in default l2c_aux

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20200622175031.GA29235@kozik-lap>
Date:   Mon, 22 Jun 2020 19:50:31 +0200
From:   Krzysztof Kozlowski <krzk@...nel.org>
To:     Guillaume Tucker <guillaume.tucker@...labora.com>
Cc:     Russell King <linux@...linux.org.uk>,
        Kukjin Kim <kgene@...nel.org>,
        Kyungmin Park <kyungmin.park@...sung.com>,
        linux-arm-kernel@...ts.infradead.org,
        linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org,
        kernel@...labora.com
Subject: Re: [PATCH] ARM: exynos: clear L310_AUX_CTRL_FULL_LINE_ZERO in
 default l2c_aux_val

On Fri, Jun 12, 2020 at 02:58:37PM +0100, Guillaume Tucker wrote:
> This "alert" error message can be seen on exynos4412-odroidx2:
> 
>     L2C: platform modifies aux control register: 0x02070000 -> 0x3e470001
>     L2C: platform provided aux values permit register corruption.
> 
> Followed by this plain error message:
> 
>     L2C-310: enabling full line of zeros but not enabled in Cortex-A9
> 
> To fix it, don't set the L310_AUX_CTRL_FULL_LINE_ZERO flag (bit 0) in
> the default value of l2c_aux_val.  It may instead be enabled when
> applicable by the logic in l2c310_enable() if the attribute
> "arm,full-line-zero-disable" was set in the device tree.
> 
> The initial commit that introduced this default value was in v2.6.38:
> 
>   1cf0eb799759 "ARM: S5PV310: Add L2 cache init function in cpu.c"
> 
> However, the code to set the L310_AUX_CTRL_FULL_LINE_ZERO flag and
> manage that feature was added much later and the default value was not
> updated then.  So this seems to have been a subtle oversight
> especially since enabling it only in the cache and not in the A9 core
> doesn't actually prevent the platform from running.  According to the
> TRM, the opposite would be a real issue, if the feature was enabled in
> the A9 core but not in the cache controller.
> 
> Reported-by: "kernelci.org bot" <bot@...nelci.org>
> Signed-off-by: Guillaume Tucker <guillaume.tucker@...labora.com>
> ---
>  arch/arm/mach-exynos/exynos.c | 2 +-

Thanks, applied.

Best regards,
Krzysztof