linux-kernel - [PATCH 00/10] Add CMU/RMU/DMA/MMC/I2C support for Actions Semi S500 SoCs

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Date:   Fri, 26 Jun 2020 02:34:12 +0300
From:   Cristian Ciocaltea <cristian.ciocaltea@...il.com>
To:     Rob Herring <robh+dt@...nel.org>,
        Andreas Färber <afaerber@...e.de>,
        Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc:     devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-actions@...ts.infradead.org
Subject: [PATCH 00/10] Add CMU/RMU/DMA/MMC/I2C support for Actions Semi S500 SoCs

This patchset brings a series of improvements for the Actions Semi S500
SoCs family, by adding support for Clock & Reset Management Units, DMA,
MMC & I2C controllers.

Please note the patches contain only DTS changes, but most of them
depend on previous work which is currently under review:

 - Add RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs
https://lore.kernel.org/lkml/cover.1592941257.git.cristian.ciocaltea@gmail.com/

 - Add Actions Semi S500 pinctrl support
https://lore.kernel.org/lkml/cover.1593112402.git.cristian.ciocaltea@gmail.com/

For the moment, I have only enabled the features tested on RoseapplePi,
the SBC for which an initial support has been already submitted via:
https://lore.kernel.org/lkml/cover.1592123160.git.cristian.ciocaltea@gmail.com/

Thanks,
Cristi

Cristian Ciocaltea (10):
  arm: dts: owl-s500: Add Clock Management Unit
  arm: dts: owl-s500: Set UART clock refs from CMU
  arm: dts: owl-s500: Add DMA controller
  arm: dts: owl-s500: Add Reset Controller support
  arm: dts: owl-s500: Add pinctrl node
  arm: dts: owl-s500: Add MMC nodes
  arm: dts: owl-s500: Add I2C nodes
  arm: dts: owl-s500-roseapplepi: Use UART clock from CMU
  arm: dts: owl-s500-roseapplepi: Add uSD support
  arm: dts: owl-s500-roseapplepi: Enable I2C0

 arch/arm/boot/dts/owl-s500-roseapplepi.dts |  96 ++++++++++++++-
 arch/arm/boot/dts/owl-s500.dtsi            | 130 +++++++++++++++++++++
 2 files changed, 221 insertions(+), 5 deletions(-)

-- 
2.27.0