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Date: Thu, 25 Jun 2020 12:17:56 +0200 From: Enric Balletbo i Serra <enric.balletbo@...labora.com> To: linux-kernel@...r.kernel.org Cc: Collabora Kernel ML <kernel@...labora.com>, erwanaliasr1@...il.com, matthias.bgg@...il.com, drinkcat@...omium.org, hsinyi@...omium.org, Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org Subject: [PATCH v2 6/7] arm64: dts: mt8183: Add USB3.0 support Add the USB3.0 phyter and controller for the MediaTek's MT8183 SoC. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com> --- Changes in v2: - Move adding #phy-cells to this patch. (Matthias Brugger) arch/arm64/boot/dts/mediatek/mt8183.dtsi | 58 ++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 6c00ffa275202..102105871db25 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/reset-controller/mt8183-resets.h> +#include <dt-bindings/phy/phy.h> #include "mt8183-pinfunc.h" / { @@ -648,6 +649,36 @@ i2c8: i2c@...1b000 { status = "disabled"; }; + ssusb: usb@...01000 { + compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, + <&infracfg CLK_INFRA_USB>; + clock-names = "sys_ck", "ref_ck"; + mediatek,syscon-wakeup = <&pericfg 0x400 0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host: xhci@...00000 { + compatible = "mediatek,mt8183-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, + <&infracfg CLK_INFRA_USB>; + clock-names = "sys_ck", "ref_ck"; + status = "disabled"; + }; + }; + audiosys: syscon@...20000 { compatible = "mediatek,mt8183-audiosys", "syscon"; reg = <0 0x11220000 0 0x1000>; @@ -684,6 +715,33 @@ efuse: efuse@...10000 { reg = <0 0x11f10000 0 0x1000>; }; + u3phy: usb-phy@...40000 { + compatible = "mediatek,mt8183-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #phy-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11f40000 0x1000>; + status = "okay"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,discth = <15>; + status = "okay"; + }; + + u3port0: usb-phy@...0 { + reg = <0x0700 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + mfgcfg: syscon@...00000 { compatible = "mediatek,mt8183-mfgcfg", "syscon"; reg = <0 0x13000000 0 0x1000>; -- 2.27.0
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