linux-kernel - Re: [PATCH] arm64: Add KRYO{3,4}XX silver CPU cores to SSB safelist

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Message-ID: <CAD=FV=WONg5C0Twm7b=aED21VLb6GLk4K6DMmYcSXVLAtdkUZg@mail.gmail.com>
Date:   Thu, 25 Jun 2020 06:48:03 -0700
From:   Doug Anderson <dianders@...omium.org>
To:     Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
Cc:     Will Deacon <will@...nel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Mark Rutland <mark.rutland@....com>,
        Stephen Boyd <swboyd@...omium.org>,
        Jeffrey Hugo <jhugo@...eaurora.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>
Subject: Re: [PATCH] arm64: Add KRYO{3,4}XX silver CPU cores to SSB safelist

Hi,

On Thu, Jun 25, 2020 at 3:31 AM Sai Prakash Ranjan
<saiprakash.ranjan@...eaurora.org> wrote:
>
> QCOM KRYO{3,4}XX silver/LITTLE CPU cores are based on
> Cortex-A55 and are SSB safe, hence add them to SSB
> safelist -> arm64_ssb_cpus[].
>
> Reported-by: Stephen Boyd <swboyd@...omium.org>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
> ---
>  arch/arm64/kernel/cpu_errata.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index ad06d6802d2e..cf50c53e9357 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -460,6 +460,8 @@ static const struct midr_range arm64_ssb_cpus[] = {
>         MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
>         MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
>         MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
> +       MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
> +       MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),

Reviewed-by: Douglas Anderson <dianders@...omium.org>