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Message-ID: <485fda739c9ebd157b1552ac3d114f38b702328e.camel@pengutronix.de>
Date: Fri, 26 Jun 2020 14:14:28 +0200
From: Philipp Zabel <p.zabel@...gutronix.de>
To: Cristian Ciocaltea <cristian.ciocaltea@...il.com>,
Stephen Boyd <sboyd@...nel.org>,
Andreas Färber <afaerber@...e.de>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Michael Turquette <mturquette@...libre.com>
Cc: linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-actions@...ts.infradead.org
Subject: Re: [PATCH v2 4/6] dt-bindings: reset: Add binding constants for
Actions S500 RMU
On Wed, 2020-06-24 at 20:47 +0300, Cristian Ciocaltea wrote:
> Add device tree binding constants for Actions Semi S500 SoC Reset
> Management Unit (RMU).
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@...il.com>
Acked-by: Philipp Zabel <p.zabel@...gutronix.de>
to be merged through the clock tree, required by the following patch:
"clk: actions: Add Actions S500 SoC Reset Management Unit support".
regards
Philipp
> ---
> .../dt-bindings/reset/actions,s500-reset.h | 67 +++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 include/dt-bindings/reset/actions,s500-reset.h
>
> diff --git a/include/dt-bindings/reset/actions,s500-reset.h b/include/dt-bindings/reset/actions,s500-reset.h
> new file mode 100644
> index 000000000000..f5d94176d10b
> --- /dev/null
> +++ b/include/dt-bindings/reset/actions,s500-reset.h
> @@ -0,0 +1,67 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Device Tree binding constants for Actions Semi S500 Reset Management Unit
> + *
> + * Copyright (c) 2014 Actions Semi Inc.
> + * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@...il.com>
> + */
> +
> +#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H
> +#define __DT_BINDINGS_ACTIONS_S500_RESET_H
> +
> +#define RESET_DMAC 0
> +#define RESET_NORIF 1
> +#define RESET_DDR 2
> +#define RESET_NANDC 3
> +#define RESET_SD0 4
> +#define RESET_SD1 5
> +#define RESET_PCM1 6
> +#define RESET_DE 7
> +#define RESET_LCD 8
> +#define RESET_SD2 9
> +#define RESET_DSI 10
> +#define RESET_CSI 11
> +#define RESET_BISP 12
> +#define RESET_KEY 13
> +#define RESET_GPIO 14
> +#define RESET_AUDIO 15
> +#define RESET_PCM0 16
> +#define RESET_VDE 17
> +#define RESET_VCE 18
> +#define RESET_GPU3D 19
> +#define RESET_NIC301 20
> +#define RESET_LENS 21
> +#define RESET_PERIPHRESET 22
> +#define RESET_USB2_0 23
> +#define RESET_TVOUT 24
> +#define RESET_HDMI 25
> +#define RESET_HDCP2TX 26
> +#define RESET_UART6 27
> +#define RESET_UART0 28
> +#define RESET_UART1 29
> +#define RESET_UART2 30
> +#define RESET_SPI0 31
> +#define RESET_SPI1 32
> +#define RESET_SPI2 33
> +#define RESET_SPI3 34
> +#define RESET_I2C0 35
> +#define RESET_I2C1 36
> +#define RESET_USB3 37
> +#define RESET_UART3 38
> +#define RESET_UART4 39
> +#define RESET_UART5 40
> +#define RESET_I2C2 41
> +#define RESET_I2C3 42
> +#define RESET_ETHERNET 43
> +#define RESET_CHIPID 44
> +#define RESET_USB2_1 45
> +#define RESET_WD0RESET 46
> +#define RESET_WD1RESET 47
> +#define RESET_WD2RESET 48
> +#define RESET_WD3RESET 49
> +#define RESET_DBG0RESET 50
> +#define RESET_DBG1RESET 51
> +#define RESET_DBG2RESET 52
> +#define RESET_DBG3RESET 53
> +
> +#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */
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