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Message-ID: <20200626125350.GA29985@duo.ucw.cz>
Date: Fri, 26 Jun 2020 14:53:50 +0200
From: Pavel Machek <pavel@...x.de>
To: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc: linux-kernel@...r.kernel.org, stable@...r.kernel.org,
Tomasz Maciej Nowak <tmn505@...il.com>,
Pali Rohár <pali@...nel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Rob Herring <robh@...nel.org>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Sasha Levin <sashal@...nel.org>
Subject: Re: [PATCH 4.19 023/206] PCI: aardvark: Dont blindly enable ASPM L0s
and dont write to read-only register
Hi!
> [ Upstream commit 90c6cb4a355e7befcb557d217d1d8b8bd5875a05 ]
>
> Trying to change Link Status register does not have any effect as this
> is a read-only register. Trying to overwrite bits for Negotiated Link
> Width does not make sense.
I don't quite get it. This says register is read only...
> In future proper change of link width can be done via Lane Count Select
> bits in PCIe Control 0 register.
>
> Trying to unconditionally enable ASPM L0s via ASPM Control bits in Link
> Control register is wrong. There should be at least some detection if
> endpoint supports L0s as isn't mandatory.
....and this says it is wrong to set the bits as ASPM L0 is not
mandatory.
> +++ b/drivers/pci/controller/pci-aardvark.c
> @@ -321,10 +321,6 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
>
> advk_pcie_wait_for_link(pcie);
>
> - reg = PCIE_CORE_LINK_L0S_ENTRY |
> - (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
> - advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
> -
> reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
> reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
> PCIE_CORE_CMD_IO_ACCESS_EN |
...but we only do single write.
So which is it?
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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