linux-kernel - Re: [PATCH v5 09/10] iommu/mediatek: Modify MMU

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-ID: <e063a5d2-8edc-9cf9-4872-d3f4abb1e481@gmail.com>
Date:   Mon, 29 Jun 2020 12:28:04 +0200
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     Chao Hao <chao.hao@...iatek.com>, Joerg Roedel <joro@...tes.org>,
        Rob Herring <robh+dt@...nel.org>
Cc:     Yong Wu <yong.wu@...iatek.com>, Evan Green <evgreen@...omium.org>,
        iommu@...ts.linux-foundation.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, wsd_upstream@...iatek.com,
        FY Yang <fy.yang@...iatek.com>
Subject: Re: [PATCH v5 09/10] iommu/mediatek: Modify MMU_CTRL register setting



On 29/06/2020 09:13, Chao Hao wrote:
> MT8173 is different from other SoCs for MMU_CTRL register.
> For mt8173, its bit9 is in_order_write_en and doesn't use its
> default 1'b1.> For other SoCs, bit[12] represents victim_tlb_en feature and
> victim_tlb is enable defaultly(bit[12]=1), if we use
> "regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR", victim_tlb will be
> disabled, it will drop iommu performace.
> So we need to deal with the setting of MMU_CTRL separately
> for mt8173 and others.
> 

My proposal to rewrite the commit message:

The MMU_CTRL regiser of MT8173 is different from other SoCs. The in_order_wr_en
is bit[9] which is zero by default.
Other SoCs have the vitcim_tlb_en feature mapped to bit[12]. This bit is set to
one by default. We need to preserve the bit when setting
F_MMU_TF_PROT_TO_PROGRAM_ADDR as otherwise the bit will be cleared and IOMMU
performance will drop.


> Suggested-by: Matthias Brugger <matthias.bgg@...il.com>
> Suggested-by: Yong Wu <yong.wu@...iatek.com>
> Signed-off-by: Chao Hao <chao.hao@...iatek.com>
> ---
>  drivers/iommu/mtk_iommu.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 8299a3299090..e46e2deee3fd 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -543,11 +543,12 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
>  		return ret;
>  	}
>  
> +	regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);

The read is only needed in the else branch.

>  	if (data->plat_data->m4u_plat == M4U_MT8173)
>  		regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
>  			 F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
>  	else
> -		regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR;
> +		regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
>  	writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
>  
>  	regval = F_L2_MULIT_HIT_EN |
>