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Message-ID: <20200629111458.1661446b@canb.auug.org.au>
Date: Mon, 29 Jun 2020 11:14:58 +1000
From: Stephen Rothwell <sfr@...b.auug.org.au>
To: Daniel Vetter <daniel.vetter@...ll.ch>,
Intel Graphics <intel-gfx@...ts.freedesktop.org>,
DRI <dri-devel@...ts.freedesktop.org>
Cc: Linux Next Mailing List <linux-next@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Nirmoy Das <nirmoy.aiemd@...il.com>,
Thomas Zimmermann <tzimmermann@...e.de>,
Ben Skeggs <bskeggs@...hat.com>,
Dave Airlie <airlied@...ux.ie>,
James Jones <jajones@...dia.com>,
Ralph Campbell <rcampbell@...dia.com>
Subject: linux-next: manual merge of the drm-misc tree with Linus' tree
Hi all,
Today's linux-next merge of the drm-misc tree got conflicts in:
drivers/gpu/drm/nouveau/dispnv04/crtc.c
drivers/gpu/drm/nouveau/dispnv04/overlay.c
drivers/gpu/drm/nouveau/dispnv50/base507c.c
drivers/gpu/drm/nouveau/dispnv50/wndw.c
drivers/gpu/drm/nouveau/nouveau_dmem.c
drivers/gpu/drm/nouveau/nouveau_fbcon.c
between commits:
183405879255 ("drm/nouveau/kms: Remove field nvbo from struct nouveau_framebuffer")
c586f30bf74c ("drm/nouveau/kms: Add format mod prop to base/ovly/nvdisp")
1d7f940c3a16 ("drm/nouveau/nouveau/hmm: fix nouveau_dmem_chunk allocations")
from Linus' tree and commit:
0dc9b286b8d2 ("drm/nouveau: don't use ttm bo->offset v3")
from the drm-misc tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/gpu/drm/nouveau/dispnv04/crtc.c
index 640738f3196c,cc6ab3c2eec7..000000000000
--- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
@@@ -840,12 -839,13 +840,12 @@@ nv04_crtc_do_mode_set_base(struct drm_c
*/
if (atomic) {
drm_fb = passed_fb;
- fb = nouveau_framebuffer(passed_fb);
} else {
drm_fb = crtc->primary->fb;
- fb = nouveau_framebuffer(crtc->primary->fb);
}
- nv_crtc->fb.offset = fb->nvbo->offset;
+ nvbo = nouveau_gem_object(drm_fb->obj[0]);
- nv_crtc->fb.offset = nvbo->bo.offset;
++ nv_crtc->fb.offset = nvbo->offset;
if (nv_crtc->lut.depth != drm_fb->format->depth) {
nv_crtc->lut.depth = drm_fb->format->depth;
diff --cc drivers/gpu/drm/nouveau/dispnv04/overlay.c
index 6248fd1dbc6d,9529bd9053e7..000000000000
--- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c
@@@ -152,7 -150,7 +152,7 @@@ nv10_update_plane(struct drm_plane *pla
nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0);
nvif_wr32(dev, NV_PVIDEO_BASE(flip), 0);
- nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nvbo->bo.offset);
- nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nv_fb->nvbo->offset);
++ nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nvbo->offset);
nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w);
nvif_wr32(dev, NV_PVIDEO_POINT_IN(flip), src_y << 16 | src_x);
nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w);
@@@ -174,7 -172,7 +174,7 @@@
if (format & NV_PVIDEO_FORMAT_PLANAR) {
nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0);
nvif_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip),
- nvbo->bo.offset + fb->offsets[1]);
- nv_fb->nvbo->offset + fb->offsets[1]);
++ nvbo->offset + fb->offsets[1]);
}
nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format | fb->pitches[0]);
nvif_wr32(dev, NV_PVIDEO_STOP, 0);
@@@ -399,7 -396,7 +399,7 @@@ nv04_update_plane(struct drm_plane *pla
for (i = 0; i < 2; i++) {
nvif_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i,
- nvbo->bo.offset);
- nv_fb->nvbo->offset);
++ nvbo->offset);
nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i,
fb->pitches[0]);
nvif_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0);
diff --cc drivers/gpu/drm/nouveau/dispnv50/base507c.c
index 511258bfbcbc,b60aa987d7b4..000000000000
--- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c
@@@ -274,9 -273,9 +274,9 @@@ base507c_new_(const struct nv50_wndw_fu
if (*pwndw = wndw, ret)
return ret;
- ret = nv50_dmac_create(&drm->client.device, &disp->disp->object,
+ ret = nv50_dmac_create(&drm->client.device, &disp->disp.object,
&oclass, head, &args, sizeof(args),
- disp50->sync->bo.offset, &wndw->wndw);
- disp->sync->offset, &wndw->wndw);
++ disp50->sync->offset, &wndw->wndw);
if (ret) {
NV_ERROR(drm, "base%04x allocation failed: %d\n", oclass, ret);
return ret;
diff --cc drivers/gpu/drm/nouveau/dispnv50/wndw.c
index 99b9b681736d,ee0fd817185e..000000000000
--- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c
@@@ -521,12 -507,11 +521,12 @@@ nv50_wndw_prepare_fb(struct drm_plane *
return PTR_ERR(ctxdma);
}
- asyw->image.handle[0] = ctxdma->object.handle;
+ if (asyw->visible)
+ asyw->image.handle[0] = ctxdma->object.handle;
}
- asyw->state.fence = dma_resv_get_excl_rcu(fb->nvbo->bo.base.resv);
- asyw->image.offset[0] = fb->nvbo->offset;
+ asyw->state.fence = dma_resv_get_excl_rcu(nvbo->bo.base.resv);
- asyw->image.offset[0] = nvbo->bo.offset;
++ asyw->image.offset[0] = nvbo->offset;
if (wndw->func->prepare) {
asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
diff --cc drivers/gpu/drm/nouveau/nouveau_dmem.c
index e5c230d9ae24,f13086a32f0f..000000000000
--- a/drivers/gpu/drm/nouveau/nouveau_dmem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c
@@@ -75,32 -72,25 +75,32 @@@ struct nouveau_dmem_migrate
struct nouveau_dmem {
struct nouveau_drm *drm;
- struct dev_pagemap pagemap;
struct nouveau_dmem_migrate migrate;
- struct list_head chunk_free;
- struct list_head chunk_full;
- struct list_head chunk_empty;
+ struct list_head chunks;
struct mutex mutex;
+ struct page *free_pages;
+ spinlock_t lock;
};
-static inline struct nouveau_dmem *page_to_dmem(struct page *page)
+static struct nouveau_dmem_chunk *nouveau_page_to_chunk(struct page *page)
{
- return container_of(page->pgmap, struct nouveau_dmem, pagemap);
+ return container_of(page->pgmap, struct nouveau_dmem_chunk, pagemap);
+}
+
+static struct nouveau_drm *page_to_drm(struct page *page)
+{
+ struct nouveau_dmem_chunk *chunk = nouveau_page_to_chunk(page);
+
+ return chunk->drm;
}
-static unsigned long nouveau_dmem_page_addr(struct page *page)
+unsigned long nouveau_dmem_page_addr(struct page *page)
{
- struct nouveau_dmem_chunk *chunk = page->zone_device_data;
- unsigned long idx = page_to_pfn(page) - chunk->pfn_first;
+ struct nouveau_dmem_chunk *chunk = nouveau_page_to_chunk(page);
+ unsigned long off = (page_to_pfn(page) << PAGE_SHIFT) -
+ chunk->pagemap.res.start;
- return chunk->bo->bo.offset + off;
- return (idx << PAGE_SHIFT) + chunk->bo->offset;
++ return chunk->bo->offset + off;
}
static void nouveau_dmem_page_free(struct page *page)
diff --cc drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 3d11b84d4cf9,1341c6fca3ed..000000000000
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@@ -393,7 -393,7 +393,7 @@@ nouveau_fbcon_create(struct drm_fb_help
/* To allow resizeing without swapping buffers */
NV_INFO(drm, "allocated %dx%d fb: 0x%llx, bo %p\n",
- fb->width, fb->height, nvbo->bo.offset, nvbo);
- fb->base.width, fb->base.height, fb->nvbo->offset, nvbo);
++ fb->width, fb->height, nvbo->offset, nvbo);
vga_switcheroo_client_fb_set(dev->pdev, info);
return 0;
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