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Message-ID: <CAGngYiXJy4ASTNfT+R+qzJ3wA=Wy2h6XZm+8oo09sD+Jmse02w@mail.gmail.com>
Date: Mon, 29 Jun 2020 09:40:38 -0400
From: Sven Van Asbroeck <thesven73@...il.com>
To: Fabio Estevam <festevam@...il.com>
Cc: Shawn Guo <shawnguo@...nel.org>, Fugang Duan <fugang.duan@....com>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
NXP Linux Team <linux-imx@....com>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 2/2] ARM: imx6plus: enable internal routing of
clk_enet_ref where possible
Hi Fabio,
On Mon, Jun 29, 2020 at 9:10 AM Fabio Estevam <festevam@...il.com> wrote:
>
> I have tested this series on an imx6qp sabresd and unfortunately, it
> breaks Ethernet as I can no longer get an IP address from the DHCP
> server.
Thank you for testing this out on a different platform !
I had a look at how things are done in the Freescale fork of the kernel
(5.4.24_2.1.0) and I noticed that this kernel has almost the same
behaviour as this proposed patch: the GPR5 bit is _always_ set
on a plus. The code does not check how the enet clock is generated.
https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm/mach-imx/mach-imx6q.c?h=rel_imx_5.4.24_2.1.0&id=babac008e5cf168abca1a85bda2e8071ca27a5c0#n269
Now, I'm assuming that the sabresd-plus can run on the Freescale
kernel fork. The GPR5 bit will always be set there.
So why won't mainline work with this patch? What have I overlooked?
I'm sure you've checked that sabresd ethernet works ok on mainline
even without this patch?
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