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Message-ID: <CAP245DV-_+5Ht=yP9Mnzb2vUqXDJSEeBPfbNh48mEt62PmBeWA@mail.gmail.com>
Date: Tue, 30 Jun 2020 11:06:56 +0530
From: Amit Kucheria <amit.kucheria@...aro.org>
To: Andy Tang <andy.tang@....com>
Cc: Shawn Guo <shawnguo@...nel.org>, Leo Li <leoyang.li@....com>,
Rob Herring <robh+dt@...nel.org>,
lakml <linux-arm-kernel@...ts.infradead.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>, LKML <linux-kernel@...r.kernel.org>
Subject: Re: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more thermal zone support
On Tue, Jun 30, 2020 at 10:58 AM Andy Tang <andy.tang@....com> wrote:
>
>
>
> > -----Original Message-----
> > From: Amit Kucheria <amit.kucheria@...aro.org>
> > Sent: 2020年6月30日 13:12
> > To: Andy Tang <andy.tang@....com>
> > Cc: Shawn Guo <shawnguo@...nel.org>; Leo Li <leoyang.li@....com>; Rob
> > Herring <robh+dt@...nel.org>; lakml <linux-arm-kernel@...ts.infradead.org>;
> > open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> > <devicetree@...r.kernel.org>; LKML <linux-kernel@...r.kernel.org>
> > Subject: [EXT] Re: [PATCH 1/2] arm64: dts: ls1088a: add more thermal zone
> > support
> >
> > Caution: EXT Email
> >
> > On Tue, Jun 30, 2020 at 8:56 AM <andy.tang@....com> wrote:
> > >
> > > From: Yuantian Tang <andy.tang@....com>
> > >
> > > There are 2 thermal zones in ls1088a soc. Add the other thermal zone
> > > node to enable it.
> > > Also update the values in calibration table to make the temperatures
> > > monitored more precise.
> > >
> > > Signed-off-by: Yuantian Tang <andy.tang@....com>
> > > ---
> > > .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 100
> > > +++++++++++-------
> > > 1 file changed, 62 insertions(+), 38 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > index 36a799554620..ccbbc23e6c85 100644
> > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > > @@ -129,19 +129,19 @@
> > > };
> > >
> > > thermal-zones {
> > > - cpu_thermal: cpu-thermal {
> > > + core-cluster {
> > > polling-delay-passive = <1000>;
> > > polling-delay = <5000>;
> > > thermal-sensors = <&tmu 0>;
> > >
> > > trips {
> > > - cpu_alert: cpu-alert {
> > > + core_cluster_alert:
> > core-cluster-alert
> > > + {
> > > temperature = <85000>;
> > > hysteresis = <2000>;
> > > type = "passive";
> > > };
> > >
> > > - cpu_crit: cpu-crit {
> > > + core_cluster_crit: core-cluster-crit {
> > > temperature = <95000>;
> > > hysteresis = <2000>;
> > > type = "critical"; @@
> > -150,7
> > > +150,7 @@
> > >
> > > cooling-maps {
> > > map0 {
> > > - trip = <&cpu_alert>;
> > > + trip =
> > <&core_cluster_alert>;
> > > cooling-device =
> > > <&cpu0
> > THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > > <&cpu1
> > > THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -163,6 +163,26 @@
> > > };
> > > };
> > > };
> > > +
> > > + soc {
> > > + polling-delay-passive = <1000>;
> > > + polling-delay = <5000>;
> > > + thermal-sensors = <&tmu 1>;
> > > +
> > > + trips {
> > > + soc-alert {
> > > + temperature = <85000>;
> > > + hysteresis = <2000>;
> > > + type = "passive";
> > > + };
> > > +
> > > + soc-crit {
> > > + temperature = <95000>;
> > > + hysteresis = <2000>;
> > > + type = "critical";
> > > + };
> > > + };
> > > + };
> >
> > You should also add a cooling-maps section for this thermal zone given that it
> > has a passive trip type. Otherwise there is no use for a passive trip type.
> It is better to have a cooling device. But there is only one cooling device on this platform
> which is used by core-cluster. So there is no extra cooling device for it.
> This zone can take action when critical temp is reached. So it is still useful.
> What do you suggest?
If the action taken by the core-cluster cooling-maps is the only one
that can be taken, I suggest getting rid of the the soc-alert passive
trip completely. It is not of any use.
If there is a chance that your soc thermal-zone can heat up before
your cpu-cluster zone (unlikely), you could use the same cooling
device (cpu0, cpu1) for soc thermal zone too.
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