linux-kernel - Re: [PATCH v5 4/6] memory: stm32-fmc2-ebi: add STM32 FMC2 EBI controller driver

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Message-ID: <1839269888.74591.1593509977137.JavaMail.zimbra@nod.at>
Date:   Tue, 30 Jun 2020 11:39:37 +0200 (CEST)
From:   Richard Weinberger <richard@....at>
To:     Christophe Kerello <christophe.kerello@...com>
Cc:     Richard Weinberger <richard.weinberger@...il.com>,
        Miquel Raynal <miquel.raynal@...tlin.com>,
        Vignesh Raghavendra <vigneshr@...com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>, arnd@...aro.org,
        Alexandre Torgue <alexandre.torgue@...com>,
        Marek Vasut <marex@...x.de>,
        devicetree <devicetree@...r.kernel.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        linux-mtd <linux-mtd@...ts.infradead.org>,
        linux-stm32@...md-mailman.stormreply.com
Subject: Re: [PATCH v5 4/6] memory: stm32-fmc2-ebi: add STM32 FMC2 EBI
 controller driver

----- Ursprüngliche Mail -----
> Von: "Christophe Kerello" <christophe.kerello@...com>
> An: "Richard Weinberger" <richard.weinberger@...il.com>
> CC: "Miquel Raynal" <miquel.raynal@...tlin.com>, "richard" <richard@....at>, "Vignesh Raghavendra" <vigneshr@...com>,
> "Rob Herring" <robh+dt@...nel.org>, "Mark Rutland" <mark.rutland@....com>, arnd@...aro.org, "Alexandre Torgue"
> <alexandre.torgue@...com>, "Marek Vasut" <marex@...x.de>, "devicetree" <devicetree@...r.kernel.org>, "linux-kernel"
> <linux-kernel@...r.kernel.org>, "linux-mtd" <linux-mtd@...ts.infradead.org>, linux-stm32@...md-mailman.stormreply.com
> Gesendet: Dienstag, 30. Juni 2020 11:35:38
> Betreff: Re: [PATCH v5 4/6] memory: stm32-fmc2-ebi: add STM32 FMC2 EBI controller driver

> Hi Richard,
> 
> On 6/30/20 11:13 AM, Richard Weinberger wrote:
>> On Fri, Jun 12, 2020 at 5:24 PM Christophe Kerello
>> <christophe.kerello@...com> wrote:
>>>
>>> The driver adds the support for the STMicroelectronics FMC2 EBI controller
>>> found on STM32MP SOCs.
>>>
>>> Signed-off-by: Christophe Kerello <christophe.kerello@...com>
>>> ---
>>> +       if (!IS_ERR(rstc)) {
>>> +               reset_control_assert(rstc);
>>> +               reset_control_deassert(rstc);
>> 
>> Shouldn't there be a small delay between assert and deassert?
>> Other than that the code looks good to me.
>> 
> 
> Even if I have currently not met any issue, I will add a udelay(2) to be
> safe. It will be part of v6.

Well, if it works and you are sure, please go for it. Like I said, I'm no expert in
this.
I just noticed that other users add a delay and wondered.

Thanks,
//richard