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Message-ID: <159361039503.4006.17824211510339513520.tip-bot2@tip-bot2>
Date: Wed, 01 Jul 2020 13:33:15 -0000
From: "tip-bot2 for Andy Lutomirski" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Andy Lutomirski <luto@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>, x86 <x86@...nel.org>,
LKML <linux-kernel@...r.kernel.org>
Subject: [tip: x86/fsgsbase] x86/fsgsbase: Fix Xen PV support
The following commit has been merged into the x86/fsgsbase branch of tip:
Commit-ID: d029bff60aa6c7eab281d52602b6a7a971615324
Gitweb: https://git.kernel.org/tip/d029bff60aa6c7eab281d52602b6a7a971615324
Author: Andy Lutomirski <luto@...nel.org>
AuthorDate: Fri, 26 Jun 2020 10:24:30 -07:00
Committer: Thomas Gleixner <tglx@...utronix.de>
CommitterDate: Wed, 01 Jul 2020 15:27:20 +02:00
x86/fsgsbase: Fix Xen PV support
On Xen PV, SWAPGS doesn't work. Teach __rdfsbase_inactive() and
__wrgsbase_inactive() to use rdmsrl()/wrmsrl() on Xen PV. The Xen
pvop code will understand this and issue the correct hypercalls.
Signed-off-by: Andy Lutomirski <luto@...nel.org>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Link: https://lkml.kernel.org/r/f07c08f178fe9711915862b656722a207cd52c28.1593192140.git.luto@kernel.org
---
arch/x86/kernel/process_64.c | 24 ++++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index cb8e37d..e14476f 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -163,9 +163,15 @@ static noinstr unsigned long __rdgsbase_inactive(void)
lockdep_assert_irqs_disabled();
- native_swapgs();
- gsbase = rdgsbase();
- native_swapgs();
+ if (!static_cpu_has(X86_FEATURE_XENPV)) {
+ native_swapgs();
+ gsbase = rdgsbase();
+ native_swapgs();
+ } else {
+ instrumentation_begin();
+ rdmsrl(MSR_KERNEL_GS_BASE, gsbase);
+ instrumentation_end();
+ }
return gsbase;
}
@@ -182,9 +188,15 @@ static noinstr void __wrgsbase_inactive(unsigned long gsbase)
{
lockdep_assert_irqs_disabled();
- native_swapgs();
- wrgsbase(gsbase);
- native_swapgs();
+ if (!static_cpu_has(X86_FEATURE_XENPV)) {
+ native_swapgs();
+ wrgsbase(gsbase);
+ native_swapgs();
+ } else {
+ instrumentation_begin();
+ wrmsrl(MSR_KERNEL_GS_BASE, gsbase);
+ instrumentation_end();
+ }
}
/*
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