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Message-Id: <20200702175352.19223-2-TheSven73@gmail.com>
Date: Thu, 2 Jul 2020 13:53:51 -0400
From: Sven Van Asbroeck <thesven73@...il.com>
To: shawnguo@...nel.org, fugang.duan@....com, robh+dt@...nel.org
Cc: "David S. Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>, netdev@...r.kernel.org,
devicetree@...r.kernel.org, Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH v5 2/3] dt-bindings: fec: add fsl,ptpclk-bypass-pad boolean property
If present, sources the fec's PTP clock straight from
the enet PLL, instead of having to be routed via a SoC pad.
This is only possible on certain SoCs, notably the imx6 (quad) plus.
Signed-off-by: Sven Van Asbroeck <TheSven73@...il.com>
---
Tree: v5.8-rc3
Patch history: see [PATCH v5 3/3]
To: Shawn Guo <shawnguo@...nel.org>
To: Andy Duan <fugang.duan@....com>
To: Rob Herring <robh+dt@...nel.org>
Cc: "David S. Miller" <davem@...emloft.net>
Cc: Jakub Kicinski <kuba@...nel.org>
Cc: netdev@...r.kernel.org
Cc: devicetree@...r.kernel.org
Cc: Sascha Hauer <s.hauer@...gutronix.de>
Cc: Pengutronix Kernel Team <kernel@...gutronix.de>
Cc: Fabio Estevam <festevam@...il.com>
Cc: NXP Linux Team <linux-imx@....com>
Cc: linux-arm-kernel@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org
Documentation/devicetree/bindings/net/fsl-fec.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
index 9b543789cd52..e34df25a38f6 100644
--- a/Documentation/devicetree/bindings/net/fsl-fec.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
@@ -39,6 +39,9 @@ Optional properties:
tx/rx queues 1 and 2. "int0" will be used for queue 0 and ENET_MII interrupts.
For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse
per second interrupt associated with 1588 precision time protocol(PTP).
+- fsl,ptpclk-bypass-pad: If present, sources the fec's PTP clock straight from
+ the enet PLL, instead of having to be routed via a SoC pad. This is only
+ possible on certain SoCs, notably the imx6 (quad) plus.
Optional subnodes:
- mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
--
2.17.1
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