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Date: Thu, 2 Jul 2020 22:16:29 +0200 From: Tomasz Nowicki <tn@...ihalf.com> To: will@...nel.org, robin.murphy@....com, joro@...tes.org, gregory.clement@...tlin.com, robh+dt@...nel.org, hannah@...vell.com Cc: linux-kernel@...r.kernel.org, iommu@...ts.linux-foundation.org, devicetree@...r.kernel.org, catalin.marinas@....com, nadavh@...vell.com, linux-arm-kernel@...ts.infradead.org, mw@...ihalf.com, Tomasz Nowicki <tn@...ihalf.com> Subject: [PATCH v3 0/4] Add system mmu support for Armada-806 There were already two versions of series to support SMMU for AP806, including workaround for accessing ARM SMMU 64bit registers. First [1] by Hanna Hawa and second [2] by Gregory CLEMENT. Since it got stuck this is yet another try. I incorporated the V2 comments, mainly by moving workaround code to arm-smmu-impl.c as requested. For the record, AP-806 can't access SMMU registers with 64bit width, this patches split the readq/writeq into two 32bit accesses instead and update DT bindings. The series was successfully tested on a vanilla v5.8-rc3 kernel and Intel e1000e PCIe NIC. The same for platform devices like SATA and USB. [1]: https://lkml.org/lkml/2018/10/15/373 [2]: https://lkml.org/lkml/2019/7/11/426 Hanna Hawa (1): iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743 Marcin Wojtas (1): arm64: dts: marvell: add SMMU support Tomasz Nowicki (2): iommu/arm-smmu: Add SMMU ID2 register fixup hook dt-bindings: arm-smmu: add compatible string for Marvell Armada-AP806 SMMU-500 Documentation/arm64/silicon-errata.rst | 3 ++ .../devicetree/bindings/iommu/arm,smmu.yaml | 5 ++ arch/arm64/boot/dts/marvell/armada-8040.dtsi | 36 +++++++++++++ arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 17 ++++++ drivers/iommu/arm-smmu-impl.c | 52 +++++++++++++++++++ drivers/iommu/arm-smmu.c | 3 ++ drivers/iommu/arm-smmu.h | 1 + 7 files changed, 117 insertions(+) -- 2.17.1
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