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Message-ID: <20200702101331.26375-3-lars.povlsen@microchip.com>
Date: Thu, 2 Jul 2020 12:13:25 +0200
From: Lars Povlsen <lars.povlsen@...rochip.com>
To: Mark Brown <broonie@...nel.org>, Peter Rosin <peda@...ntia.se>
CC: Lars Povlsen <lars.povlsen@...rochip.com>,
Microchip Linux Driver Support <UNGLinuxDriver@...rochip.com>,
<linux-spi@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
Serge Semin <fancer.lancer@...il.com>,
Serge Semin <Sergey.Semin@...kalelectronics.ru>
Subject: [PATCH v3 2/8] arm64: dts: sparx5: Add SPI controller and SPI mux
This adds a SPI controller to the Microchip Sparx5 SoC, as well as the
SPI bus interface mux, which may optionally be needed for selecting
between alternate SPI bus segments (SPI/SPI2).
Signed-off-by: Lars Povlsen <lars.povlsen@...rochip.com>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 7e811e24f0e99..2831935a489e1 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -14,6 +14,8 @@ / {
#size-cells = <1>;
aliases {
+ mux = &mux;
+ spi0 = &spi0;
serial0 = &uart0;
serial1 = &uart1;
};
@@ -155,6 +157,27 @@ uart1: serial@...102000 {
status = "disabled";
};
+ mux: mux-controller {
+ compatible = "microchip,sparx5-spi-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #mux-control-cells = <0>;
+ };
+
+ spi0: spi@...104000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "microchip,sparx5-spi";
+ reg = <0x6 0x00104000 0x40>;
+ num-cs = <16>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ mux-controls = <&mux>;
+ status = "disabled";
+ };
+
timer1: timer@...105000 {
compatible = "snps,dw-apb-timer";
reg = <0x6 0x00105000 0x1000>;
--
2.27.0
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