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Date: Thu, 2 Jul 2020 20:57:09 +0800 From: Hanks Chen <hanks.chen@...iatek.com> To: Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh+dt@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Sean Wang <sean.wang@...nel.org> CC: mtk01761 <wendell.lin@...iatek.com>, Andy Teng <andy.teng@...iatek.com>, <linux-gpio@...r.kernel.org>, <devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, <linux-mediatek@...ts.infradead.org>, <linux-kernel@...r.kernel.org>, <wsd_upstream@...iatek.com>, CC Hwang <cc.hwang@...iatek.com>, Loda Chou <loda.chou@...iatek.com>, Hanks Chen <hanks.chen@...iatek.com> Subject: [PATCH v7 6/7] clk: mediatek: add UART0 clock support Add MT6779 UART0 clock support. Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") Signed-off-by: Wendell Lin <wendell.lin@...iatek.com> Signed-off-by: Hanks Chen <hanks.chen@...iatek.com> --- drivers/clk/mediatek/clk-mt6779.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 9766ccc..6e0d3a1 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -919,6 +919,8 @@ "pwm_sel", 19), GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", + "uart_sel", 22), GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", -- 1.7.9.5
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