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Message-Id: <159379155800.20268.8910088727326709928.b4-ty@arm.com>
Date:   Fri,  3 Jul 2020 16:55:03 +0100
From:   Catalin Marinas <catalin.marinas@....com>
To:     Anshuman Khandual <anshuman.khandual@....com>,
        linux-arm-kernel@...ts.infradead.org
Cc:     Will Deacon <will@...nel.org>, kvmarm@...ts.cs.columbia.edu,
        Mark Rutland <mark.rutland@....com>,
        Marc Zyngier <maz@...nel.org>,
        James Morse <james.morse@....com>,
        linux-kernel@...r.kernel.org,
        Suzuki K Poulose <suzuki.poulose@....com>
Subject: Re: [PATCH V5 (RESEND) 0/4] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes

On Fri, 3 Jul 2020 09:21:33 +0530, Anshuman Khandual wrote:
> These are remaining patches from V4 series which had some pending reviews
> from Suzuki (https://patchwork.kernel.org/cover/11557333/). Also dropped
> [PATCH 15/17] as that will need some more investigation and rework.
> 
> This series applies on 5.8-rc3.
> 
> Cc: Catalin Marinas <catalin.marinas@....com>
> Cc: Will Deacon <will@...nel.org>
> Cc: Mark Rutland <mark.rutland@....com>
> Cc: Marc Zyngier <maz@...nel.org>
> Cc: James Morse <james.morse@....com>
> Cc: Suzuki K Poulose <suzuki.poulose@....com>
> Cc: kvmarm@...ts.cs.columbia.edu
> Cc: linux-arm-kernel@...ts.infradead.org
> Cc: linux-kernel@...r.kernel.org
> 
> [...]

Applied to arm64 (for-next/cpufeature), thanks!

[1/4] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register
      https://git.kernel.org/arm64/c/bc67f10ad1d7
[2/4] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register
      https://git.kernel.org/arm64/c/853772ba8023
[3/4] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register
      https://git.kernel.org/arm64/c/356fdfbe8761
[4/4] arm64/cpufeature: Replace all open bits shift encodings with macros
      https://git.kernel.org/arm64/c/8d3154afc10d

-- 
Catalin

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