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Message-Id: <20200703162548.19953-1-will@kernel.org>
Date:   Fri,  3 Jul 2020 17:25:48 +0100
From:   Will Deacon <will@...nel.org>
To:     iommu@...ts.linux-foundation.org
Cc:     linux-kernel@...r.kernel.org, kernel-team@...roid.com,
        Will Deacon <will@...nel.org>,
        Robin Murphy <robin.murphy@....com>,
        "Isaac J. Manjarres" <isaacm@...eaurora.org>,
        Joerg Roedel <joro@...tes.org>, Christoph Hellwig <hch@....de>,
        Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>,
        Rob Clark <robdclark@...il.com>
Subject: [PATCH] iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag

The IOMMU_SYS_CACHE_ONLY flag was never exposed via the DMA API and
has no in-tree users. Remove it.

Cc: Robin Murphy <robin.murphy@....com>
Cc: "Isaac J. Manjarres" <isaacm@...eaurora.org>
Cc: Joerg Roedel <joro@...tes.org>
Cc: Christoph Hellwig <hch@....de>
Cc: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
Cc: Rob Clark <robdclark@...il.com>
Signed-off-by: Will Deacon <will@...nel.org>
---

As discussed in [1], sounds like this should be a domain attribute anyway
when it's needed by the GPU.

[1] https://lore.kernel.org/r/CAF6AEGsCROVTsi2R7_aUkmH9Luoc_guMR0w0KUJc2cEgpfj79w@mail.gmail.com

 drivers/iommu/io-pgtable-arm.c | 3 ---
 include/linux/iommu.h          | 6 ------
 2 files changed, 9 deletions(-)

diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 04fbd4bf0ff9..8f175c02f8e3 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -438,9 +438,6 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
 		else if (prot & IOMMU_CACHE)
 			pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
 				<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
-		else if (prot & IOMMU_SYS_CACHE_ONLY)
-			pte |= (ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE
-				<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
 	}
 
 	if (prot & IOMMU_CACHE)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 5f0b7859d2eb..bee1a8fa1fb1 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -31,12 +31,6 @@
  * if the IOMMU page table format is equivalent.
  */
 #define IOMMU_PRIV	(1 << 5)
-/*
- * Non-coherent masters can use this page protection flag to set cacheable
- * memory attributes for only a transparent outer level of cache, also known as
- * the last-level or system cache.
- */
-#define IOMMU_SYS_CACHE_ONLY	(1 << 6)
 
 struct iommu_ops;
 struct iommu_group;
-- 
2.27.0.212.ge8ba1cc988-goog

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