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Message-Id: <1593861989-35920-3-git-send-email-yi.l.liu@intel.com>
Date: Sat, 4 Jul 2020 04:26:16 -0700
From: Liu Yi L <yi.l.liu@...el.com>
To: alex.williamson@...hat.com, eric.auger@...hat.com,
baolu.lu@...ux.intel.com, joro@...tes.org
Cc: kevin.tian@...el.com, jacob.jun.pan@...ux.intel.com,
ashok.raj@...el.com, yi.l.liu@...el.com, jun.j.tian@...el.com,
yi.y.sun@...el.com, jean-philippe@...aro.org, peterx@...hat.com,
hao.wu@...el.com, stefanha@...il.com,
iommu@...ts.linux-foundation.org, kvm@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v4 02/15] iommu: Report domain nesting info
IOMMUs that support nesting translation needs report the capability info
to userspace, e.g. the format of first level/stage paging structures.
This patch reports nesting info by DOMAIN_ATTR_NESTING. Caller can get
nesting info after setting DOMAIN_ATTR_NESTING.
Cc: Kevin Tian <kevin.tian@...el.com>
CC: Jacob Pan <jacob.jun.pan@...ux.intel.com>
Cc: Alex Williamson <alex.williamson@...hat.com>
Cc: Eric Auger <eric.auger@...hat.com>
Cc: Jean-Philippe Brucker <jean-philippe@...aro.org>
Cc: Joerg Roedel <joro@...tes.org>
Cc: Lu Baolu <baolu.lu@...ux.intel.com>
Signed-off-by: Liu Yi L <yi.l.liu@...el.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@...ux.intel.com>
---
v3 -> v4:
*) split the SMMU driver changes to be a separate patch
*) move the @addr_width and @pasid_bits from vendor specific
part to generic part.
*) tweak the description for the @features field of struct
iommu_nesting_info.
*) add description on the @data[] field of struct iommu_nesting_info
v2 -> v3:
*) remvoe cap/ecap_mask in iommu_nesting_info.
*) reuse DOMAIN_ATTR_NESTING to get nesting info.
*) return an empty iommu_nesting_info for SMMU drivers per Jean'
suggestion.
---
include/uapi/linux/iommu.h | 78 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/include/uapi/linux/iommu.h b/include/uapi/linux/iommu.h
index 1afc661..1bfc032 100644
--- a/include/uapi/linux/iommu.h
+++ b/include/uapi/linux/iommu.h
@@ -332,4 +332,82 @@ struct iommu_gpasid_bind_data {
} vendor;
};
+/*
+ * struct iommu_nesting_info - Information for nesting-capable IOMMU.
+ * user space should check it before using
+ * nesting capability.
+ *
+ * @size: size of the whole structure
+ * @format: PASID table entry format, the same definition with
+ * @format of struct iommu_gpasid_bind_data.
+ * @features: supported nesting features.
+ * @flags: currently reserved for future extension.
+ * @addr_width: The output addr width of first level/stage translation
+ * @pasid_bits: Maximum supported PASID bits, 0 represents no PASID
+ * support.
+ * @data: vendor specific cap info. data[] structure type can be deduced
+ * from @format field.
+ *
+ * +===============+======================================================+
+ * | feature | Notes |
+ * +===============+======================================================+
+ * | SYSWIDE_PASID | PASIDs are managed in system-wide, instead of per |
+ * | | device. When a device is assigned to userspace or |
+ * | | VM, proper uAPI (userspace driver framework uAPI, |
+ * | | e.g. VFIO) must be used to allocate/free PASIDs for |
+ * | | the assigned device. |
+ * +---------------+------------------------------------------------------+
+ * | BIND_PGTBL | The owner of the first level/stage page table must |
+ * | | explicitly bind the page table to associated PASID |
+ * | | (either the one specified in bind request or the |
+ * | | default PASID of iommu domain), through userspace |
+ * | | driver framework uAPI (e.g. VFIO_IOMMU_NESTING_OP). |
+ * +---------------+------------------------------------------------------+
+ * | CACHE_INVLD | The owner of the first level/stage page table must |
+ * | | explicitly invalidate the IOMMU cache through uAPI |
+ * | | provided by userspace driver framework (e.g. VFIO) |
+ * | | according to vendor-specific requirement when |
+ * | | changing the page table. |
+ * +---------------+------------------------------------------------------+
+ *
+ * @data[] types defined for @format:
+ * +================================+=====================================+
+ * | @format | @data[] |
+ * +================================+=====================================+
+ * | IOMMU_PASID_FORMAT_INTEL_VTD | struct iommu_nesting_info_vtd |
+ * +--------------------------------+-------------------------------------+
+ *
+ */
+struct iommu_nesting_info {
+ __u32 size;
+ __u32 format;
+ __u32 features;
+#define IOMMU_NESTING_FEAT_SYSWIDE_PASID (1 << 0)
+#define IOMMU_NESTING_FEAT_BIND_PGTBL (1 << 1)
+#define IOMMU_NESTING_FEAT_CACHE_INVLD (1 << 2)
+ __u32 flags;
+ __u16 addr_width;
+ __u16 pasid_bits;
+ __u32 padding;
+ __u8 data[];
+};
+
+/*
+ * struct iommu_nesting_info_vtd - Intel VT-d specific nesting info
+ *
+ *
+ * @flags: VT-d specific flags. Currently reserved for future
+ * extension.
+ * @cap_reg: Describe basic capabilities as defined in VT-d capability
+ * register.
+ * @ecap_reg: Describe the extended capabilities as defined in VT-d
+ * extended capability register.
+ */
+struct iommu_nesting_info_vtd {
+ __u32 flags;
+ __u32 padding;
+ __u64 cap_reg;
+ __u64 ecap_reg;
+};
+
#endif /* _UAPI_IOMMU_H */
--
2.7.4
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