linux-kernel - [PATCH 3/9] clk: qcom: ipq8074: Add missing bindings for pcie

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <1593940680-2363-4-git-send-email-sivaprak@codeaurora.org>
Date:   Sun,  5 Jul 2020 14:47:54 +0530
From:   Sivaprakash Murugesan <sivaprak@...eaurora.org>
To:     agross@...nel.org, bjorn.andersson@...aro.org, bhelgaas@...gle.com,
        robh+dt@...nel.org, kishon@...com, vkoul@...nel.org,
        mturquette@...libre.com, sboyd@...nel.org, svarbanov@...sol.com,
        lorenzo.pieralisi@....com, p.zabel@...gutronix.de,
        sivaprak@...eaurora.org, mgautam@...eaurora.org,
        smuthayy@...eaurora.org, varada@...eaurora.org,
        linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org
Cc:     Selvam Sathappan Periakaruppan <speriaka@...eaurora.org>
Subject: [PATCH 3/9] clk: qcom: ipq8074: Add missing bindings for pcie

Add missing clock bindings for pcie port0 of ipq8074.

Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@...eaurora.org>
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@...eaurora.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@...eaurora.org>
---
 include/dt-bindings/clock/qcom,gcc-ipq8074.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
index 4de4811a3540..e3e018565add 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -362,5 +362,9 @@
 #define GCC_PCIE1_AXI_SLAVE_ARES		128
 #define GCC_PCIE1_AHB_ARES			129
 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES	130
+#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES		131
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK		132
+#define GCC_PCIE0_RCHNG_CLK_SRC			133
+#define GCC_PCIE0_RCHNG_CLK			134
 
 #endif
-- 
2.7.4