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Message-ID: <AM6PR0402MB360781DA3F738C2DF445E821FF680@AM6PR0402MB3607.eurprd04.prod.outlook.com>
Date: Sun, 5 Jul 2020 14:45:02 +0000
From: Andy Duan <fugang.duan@....com>
To: Sven Van Asbroeck <thesven73@...il.com>,
Fabio Estevam <festevam@...il.com>
CC: Shawn Guo <shawnguo@...nel.org>, Rob Herring <robh+dt@...nel.org>,
"David S. Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
netdev <netdev@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
dl-linux-imx <linux-imx@....com>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>
Subject: RE: [EXT] Re: [PATCH v5 3/3] ARM: imx6plus: optionally enable
internal routing of clk_enet_ref
From: Sven Van Asbroeck <thesven73@...il.com>
> Hi Fabio, Andy,
>
> On Thu, Jul 2, 2020 at 6:29 PM Fabio Estevam <festevam@...il.com> wrote:
> >
> > With the device tree approach, I think that a better place to touch
> > GPR5 would be inside the fec driver.
> >
>
> Are we 100% sure this is the best way forward, though?
>
> All the FEC driver should care about is the FEC logic block inside the SoC. It
> should not concern itself with the way a SoC happens to bring a clock (PTP
> clock) to the input of the FEC logic block - that is purely a SoC implementation
> detail.
I also agree with that relates to SOC integration.
>
> It makes sense to add fsl,stop-mode (= a GPR bit) to the FEC driver, as this bit
> is a logic input to the FEC block, which the driver needs to dynamically flip.
>
> But the PTP clock is different, because it's statically routed by the SoC.
>
> Maybe this problem needs a clock routing solution?
> Isn't there an imx6q plus clock mux we're not modelling?
>
> enet_ref-o------>ext>---pad_clk--| \
> | |M |----fec_ptp_clk
> o-----------------------|_/
>
> Where M = mux controlled by GPR5[9]
>
> The issue here is that pad_clk is routed externally, so its parent could be any
> internal or external clock. I have no idea how to model this in the clock
> framework.
Don't consider it complex, GPR5[9] just select the rgmii gtx source from PAD or internal
Likeļ¼
GPR5[9] is cleared: PAD -> MAC gtx
GPR5[9] is set: Pll_enet -> MAC gtx
As you said, register one clock mux for the selection, assign the clock parent by board dts
file, but now current clock driver doesn't support GPR clock.
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