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Message-Id: <1593989992-10019-2-git-send-email-cathy.zhang@intel.com>
Date: Mon, 6 Jul 2020 06:59:51 +0800
From: Cathy Zhang <cathy.zhang@...el.com>
To: kvm@...r.kernel.org, linux-kernel@...r.kernel.org, x86@...nel.org
Cc: pbonzini@...hat.com, sean.j.christopherson@...el.com,
vkuznets@...hat.com, wanpengli@...cent.com, jmattson@...gle.com,
joro@...tes.org, tglx@...utronix.de, mingo@...hat.com,
bp@...en8.de, hpa@...or.com, ricardo.neri-calderon@...ux.intel.com,
kyung.min.park@...el.com, Cathy Zhang <cathy.zhang@...el.com>
Subject: [PATCH 1/2] x86: Expose SERIALIZE for supported cpuid
SERIALIZE instruction is supported by intel processors,
like Sapphire Rapids. Expose it in KVM supported cpuid.
The SERIALIZE enumeration kernel patch link is as follows:
https://lore.kernel.org/patchwork/patch/1254757/
Signed-off-by: Cathy Zhang <cathy.zhang@...el.com>
---
arch/x86/kvm/cpuid.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 8a294f9..e603aeb 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -341,7 +341,8 @@ void kvm_set_cpu_caps(void)
kvm_cpu_cap_mask(CPUID_7_EDX,
F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
- F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM)
+ F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
+ F(SERIALIZE)
);
/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
--
1.8.3.1
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