linux-kernel - Re: [PATCH] PCI: cadence: fix runtime pm imbalance on error

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Mon, 6 Jul 2020 12:12:00 +0100
From:   Lorenzo Pieralisi <lorenzo.pieralisi@....com>
To:     Dinghao Liu <dinghao.liu@....edu.cn>
Cc:     kjlu@....edu, Tom Joseph <tjoseph@...ence.com>,
        Rob Herring <robh@...nel.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] PCI: cadence: fix runtime pm imbalance on error

On Wed, May 20, 2020 at 05:02:53PM +0800, Dinghao Liu wrote:
> pm_runtime_get_sync() increments the runtime PM usage counter even
> it returns an error code. Thus a pairing decrement is needed on
> the error handling path to keep the counter balanced.
> 
> Signed-off-by: Dinghao Liu <dinghao.liu@....edu.cn>
> ---
>  drivers/pci/controller/cadence/pcie-cadence-plat.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c
> index f5c6bf6dfcb8..33c3868e6dbd 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c
> @@ -115,9 +115,8 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
>  	}
>  
>   err_init:
> -	pm_runtime_put_sync(dev);
> -
>   err_get_sync:
> +	pm_runtime_put_sync(dev);
>  	pm_runtime_disable(dev);
>  	cdns_pcie_disable_phy(cdns_plat_pcie->pcie);
>  	phy_count = cdns_plat_pcie->pcie->phy_count;

Applied to pci/runtime-pm, thanks.

Lorenzo