linux-kernel - Re: [PATCH V3 13/23] perf/x86/intel/lbr: Factor out intel_pmu_store

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Date:   Tue, 7 Jul 2020 09:40:07 +0200
From:   Peter Zijlstra <peterz@...radead.org>
To:     "Liang, Kan" <kan.liang@...ux.intel.com>
Cc:     mingo@...hat.com, acme@...nel.org, tglx@...utronix.de,
        bp@...en8.de, x86@...nel.org, linux-kernel@...r.kernel.org,
        mark.rutland@....com, alexander.shishkin@...ux.intel.com,
        jolsa@...hat.com, namhyung@...nel.org, dave.hansen@...el.com,
        yu-cheng.yu@...el.com, bigeasy@...utronix.de, gorcunov@...il.com,
        hpa@...or.com, alexey.budankov@...ux.intel.com, eranian@...gle.com,
        ak@...ux.intel.com, like.xu@...ux.intel.com,
        yao.jin@...ux.intel.com, wei.w.wang@...el.com
Subject: Re: [PATCH V3 13/23] perf/x86/intel/lbr: Factor out
 intel_pmu_store_lbr

On Mon, Jul 06, 2020 at 06:29:58PM -0400, Liang, Kan wrote:
> On 7/3/2020 4:59 PM, Liang, Kan wrote:
> > On 7/3/2020 3:50 PM, Peter Zijlstra wrote:

> > > If I'm not mistaken, this correctly deals with LBR_FORMAT_INFO, so can't
> > > we also use the intel_pmu_arch_lbr_read() function for that case?
> > 
> 
> There is another more severe issue which prevents sharing the read of Arch
> LBR with LBR_FORMAT_INFO. Sorry I missed it.

No worries, I too missed it.

> For the legacy LBR, the youngest branch is stored in TOS MSR. The next
> youngest is in (TOS - 1)...
> 
> For Arch LBR and LBR PEBS, the youngest branch is always in entry 0. The
> next youngest is in entry 1...
> 
> The growth of the legacy LBR is in a reversed order of Arch LBR and LBR
> PEBS. The legacy LBR also relies on TOS. I'm afraid we cannot use the
> intel_pmu_arch_lbr_read() function for LBR_FORMAT_INFO.
> 
> I think I will only send a patch to support NO_{CYCLES,FLAGS} for all LBR
> formats.

Thanks!