linux-kernel - RE: [EXT] Re: [PATCH v5 3/3] ARM: imx6plus: optionally enable internal routing of clk_enet

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Message-ID: <AM6PR0402MB360755E7721F28A2CE30DFE6FF670@AM6PR0402MB3607.eurprd04.prod.outlook.com>
Date:   Wed, 8 Jul 2020 05:16:47 +0000
From:   Andy Duan <fugang.duan@....com>
To:     Sven Van Asbroeck <thesven73@...il.com>
CC:     Fabio Estevam <festevam@...il.com>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        dl-linux-imx <linux-imx@....com>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        Michael Turquette <mturquette@...libre.com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>
Subject: RE: [EXT] Re: [PATCH v5 3/3] ARM: imx6plus: optionally enable
 internal routing of clk_enet_ref

From: Sven Van Asbroeck <thesven73@...il.com> Sent: Tuesday, July 7, 2020 11:21 PM
> Andy, Fabio,
> 
> Sounds like we now have a solution which makes logical sense, although it
> requires changes and additions to drivers/clk/imx/. Before I create a patch,
> can you read the plan below and check that it makes sense, please?
> 
> Problem
> =======
> On the imx6q plus, the NXP hw designers introduced an alternative way to
> clock the built-in ethernet (FEC). One single customer (archronix) seems to be
> currently using this functionality, and would like to add mainline support.
> 
> Changing the ethernet (FEC) driver appears illogical, as this change is
> unrelated to the FEC itself: fundamentally, it's a clock tree change.
> 
> We also need to prevent breaking existing boards with mis-configured FEC
> clocking:
> 
> Some board designers indicate in the devicetree that ENET_REF_CLK is
> connected to the FEC ptp clock, but in reality, they are providing an unrelated
> external clock through the pad. This will work in many cases, because the FEC
> driver does not really care where its PTP clock comes from, and the enet ref
> clock is set up to mirror the external clk frequency by the NXP U-Boot fork.
> 
> Proposed changes must not break these cases.
> 
> Proposed Solution
> =================
> On non-plus imx6q there are no changes. On imx6q plus however:
> 
> Create two new clocks (mac_gtx and pad) and a new clock mux:
> 
>   enet_ref-o--------->pad----->| \
>            |                   |  |
>            |                   |M1|----mac_gtx --- to FEC
>            |                   |  |
>            o-------------------|_/
> 
> The defaults (indicated with ">") are carefully chosen, so these changes will
> not break any existing plus designs.
> 
> We then tie the gtx clock to the FEC driver ptp clock, like so:
> 
> in imx6qp.dtsi:
> &fec {
>     clocks = <&clks IMX6QDL_CLK_ENET>,
>         <&clks IMX6QDL_CLK_ENET>,
>         <&clks IMX6QDL_CLK_MAC_GTX>;
> };
> 
> Mux M1 is controlled by GPR5[9]. This mux can just write to the GPR5
> memory address. However, the GPR registers are already exposed as a mux
> controller compatible = "mmio-mux". This mux does currently not use GPR5.
> 
> So we have to make a choice here: write straight to the memory address
> (easy), or create a new clock mux type, which uses an underlying mux
> controller.
> 
> When that is done, board designers can choose between:
> 
> 1. internal clocking (GTX clock routed internally)
> 
> &fec {
>     assigned-clocks = <&clks IMX6QDL_CLK_MAC_GTX>;
>     assigned-clock-parents = <&clks IMX6QDL_CLK_ENET_REF>; };

The one is our requirement that gtx is from internal pll and only for
6qp boards. It is required to set in board dts file due to depends on board
design.

Here also need to assign enet_ref clk rate to 125Mhz.
> 
> 2. external clocking (GTX clock from pad, pad connected to enet_ref,
>    typically via GPIO_16). This is the default and does not need to be
> present.
> 
> &fec {
>     assigned-clocks = <&clks IMX6QDL_CLK_MAC_GTX>;
>     assigned-clock-parents = <&clks IMX6QDL_CLK_PAD>; };
> 
As above, here also need to assign the enet_ref clk rate to 125Mhz.
The clk tree:
Pll6 -> enet_ref -> clk_pad -> mac_gtx
Pll6 -> enet_ref -> clk_pad -> route back to supply clk for ptp

> 
> 3. external clocking (GTX clock from pad, pad connected to external PHY
>    clock or external oscillator).
> 
> phy_osc: oscillator {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> clock-frequency = <50000000>;
> };
> 
> &fec {
>     clocks = <&clks IMX6QDL_CLK_ENET>,
>         <&clks IMX6QDL_CLK_ENET>,
>         <&phy_osc>;
> };