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Message-ID: <20200709225759.GA1040142@bogus>
Date: Thu, 9 Jul 2020 16:57:59 -0600
From: Rob Herring <robh@...nel.org>
To: Laurentiu Palcu <laurentiu.palcu@....nxp.com>
Cc: Philipp Zabel <p.zabel@...gutronix.de>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>,
Laurentiu Palcu <laurentiu.palcu@....com>,
l.stach@...gutronix.de, lukas@...mn.com, agx@...xcpu.org,
dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v5 4/5] dt-bindings: display: imx: add bindings for DCSS
On Thu, Jul 09, 2020 at 07:47:32PM +0300, Laurentiu Palcu wrote:
> From: Laurentiu Palcu <laurentiu.palcu@....com>
>
> Add bindings for iMX8MQ Display Controller Subsystem.
>
> Signed-off-by: Laurentiu Palcu <laurentiu.palcu@....com>
> ---
> .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 84 +++++++++++++++++++
> 1 file changed, 84 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> new file mode 100644
> index 000000000000..a951409cf76d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> @@ -0,0 +1,84 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2019 NXP
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: iMX8MQ Display Controller Subsystem (DCSS)
> +
> +maintainers:
> + - Laurentiu Palcu <laurentiu.palcu@....com>
> +
> +description:
> +
> + The DCSS (display controller sub system) is used to source up to three
> + display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
> + 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
> + image processing capabilities are included to provide a solution capable of
> + driving next generation high dynamic range displays.
> +
> +properties:
> + compatible:
> + const: nxp,imx8mq-dcss
> +
> + reg:
> + items:
> + - description: DCSS base address and size, up to IRQ steer start
> + - description: DCSS BLKCTL base address and size
> +
> + interrupts:
> + items:
> + - description: Context loader completion and error interrupt
> + - description: DTG interrupt used to signal context loader trigger time
> + - description: DTG interrupt for Vblank
> +
> + interrupt-names:
> + items:
> + - const: ctxld
> + - const: ctxld_kick
> + - const: vblank
> +
> + clocks:
> + items:
> + - description: Display APB clock for all peripheral PIO access interfaces
> + - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
> + - description: RTRAM clock
> + - description: Pixel clock, can be driver either by HDMI phy clock or MIPI
> + - description: DTRC clock, needed by video decompressor
> +
> + clock-names:
> + items:
> + - const: apb
> + - const: axi
> + - const: rtrm
> + - const: pix
> + - const: dtrc
> +
> + port:
> + type: object
> + description:
> + A port node pointing to the input port of a HDMI/DP or MIPI display bridge.
additionalProperties: false
With that,
Reviewed-by: Rob Herring <robh@...nel.org>
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