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Message-Id: <1594299795-39394-1-git-send-email-qianjun.kernel@gmail.com>
Date: Thu, 9 Jul 2020 21:03:15 +0800
From: qianjun <qianjun.kernel@...il.com>
To: peterz@...radead.org, mingo@...hat.com, acme@...nel.org
Cc: linux-kernel@...r.kernel.org, qianjun <qianjun@...iglobal.com>
Subject: [PATCH] perf-c2c: Fix the wrong description.
From: qianjun <qianjun@...iglobal.com>
Use L1Miss to replace L1Hit to describe the correct scene
Signed-off-by: qianjun <qianjun@...iglobal.com>
---
tools/perf/Documentation/perf-c2c.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/Documentation/perf-c2c.txt b/tools/perf/Documentation/perf-c2c.txt
index 98efdab..083e99a 100644
--- a/tools/perf/Documentation/perf-c2c.txt
+++ b/tools/perf/Documentation/perf-c2c.txt
@@ -186,7 +186,7 @@ For each cacheline in the 1) list we display following data:
Store Reference - Total, L1Hit, L1Miss
Total - all store accesses
L1Hit - store accesses that hit L1
- L1Hit - store accesses that missed L1
+ L1Miss - store accesses that missed L1
Load Dram
- count of local and remote DRAM accesses
--
1.8.3.1
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