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Message-ID: <af6ac772-318d-aab0-ce5f-55cf92f6e96d@intel.com>
Date:   Thu, 9 Jul 2020 08:56:39 -0700
From:   Dave Hansen <dave.hansen@...el.com>
To:     "Andersen, John" <john.s.andersen@...el.com>,
        Paolo Bonzini <pbonzini@...hat.com>
Cc:     Sean Christopherson <sean.j.christopherson@...el.com>,
        corbet@....net, tglx@...utronix.de, mingo@...hat.com, bp@...en8.de,
        x86@...nel.org, hpa@...or.com, shuah@...nel.org,
        liran.alon@...cle.com, drjones@...hat.com,
        rick.p.edgecombe@...el.com, kristen@...ux.intel.com,
        vkuznets@...hat.com, wanpengli@...cent.com, jmattson@...gle.com,
        joro@...tes.org, mchehab+huawei@...nel.org,
        gregkh@...uxfoundation.org, paulmck@...nel.org,
        pawan.kumar.gupta@...ux.intel.com, jgross@...e.com,
        mike.kravetz@...cle.com, oneukum@...e.com, luto@...nel.org,
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        dave.hansen@...ux.intel.com, arjan@...ux.intel.com,
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        keescook@...omium.org, dan.j.williams@...el.com,
        eric.auger@...hat.com, aaronlewis@...gle.com, peterx@...hat.com,
        makarandsonare@...gle.com, linux-doc@...r.kernel.org,
        linux-kernel@...r.kernel.org, kvm@...r.kernel.org,
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        kernel-hardening@...ts.openwall.com
Subject: Re: [PATCH 2/4] KVM: x86: Introduce paravirt feature CR0/CR4 pinning

On 7/9/20 8:44 AM, Andersen, John wrote:
> 
>         Bits which are allowed to be pinned default to WP for CR0 and SMEP,
>         SMAP, and UMIP for CR4.

I think it also makes sense to have FSGSBASE in this set.

I know it hasn't been tested, but I think we should do the legwork to
test it.  If not in this set, can we agree that it's a logical next step?

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