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Message-ID: <20200710142037.GM27672@8bytes.org>
Date: Fri, 10 Jul 2020 16:20:37 +0200
From: Joerg Roedel <joro@...tes.org>
To: Robin Murphy <robin.murphy@....com>
Cc: hch@....de, iommu@...ts.linux-foundation.org,
jonathan.lemon@...il.com, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org, baolu.lu@...ux.intel.com,
dwmw2@...radead.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 1/2] iommu/intel: Avoid SAC address trick for PCIe devices
On Wed, Jul 08, 2020 at 12:32:41PM +0100, Robin Murphy wrote:
> For devices stuck behind a conventional PCI bus, saving extra cycles at
> 33MHz is probably fairly significant. However since native PCI Express
> is now the norm for high-performance devices, the optimisation to always
> prefer 32-bit addresses for the sake of avoiding DAC is starting to look
> rather anachronistic. Technically 32-bit addresses do have shorter TLPs
> on PCIe, but unless the device is saturating its link bandwidth with
> small transfers it seems unlikely that the difference is appreciable.
>
> What definitely is appreciable, however, is that the IOVA allocator
> doesn't behave all that well once the 32-bit space starts getting full.
> As DMA working sets get bigger, this optimisation increasingly backfires
> and adds considerable overhead to the dma_map path for use-cases like
> high-bandwidth networking.
>
> As such, let's simply take it out of consideration for PCIe devices.
> Technically this might work out suboptimal for a PCIe device stuck
> behind a conventional PCI bridge, or for PCI-X devices that also have
> native 64-bit addressing, but neither of those are likely to be found
> in performance-critical parts of modern systems.
>
> Signed-off-by: Robin Murphy <robin.murphy@....com>
> ---
> drivers/iommu/intel/iommu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Applied both, thanks.
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