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Message-ID: <20200710161302.GA411219@silpixa00400314>
Date:   Fri, 10 Jul 2020 17:13:02 +0100
From:   Giovanni Cabiddu <giovanni.cabiddu@...el.com>
To:     Christoph Hellwig <hch@...radead.org>
Cc:     alex.williamson@...hat.com, herbert@...dor.apana.org.au,
        cohuck@...hat.com, nhorman@...hat.com, vdronov@...hat.com,
        bhelgaas@...gle.com, mark.a.chambers@...el.com,
        gordon.mcfadden@...el.com, ahsan.atta@...el.com,
        qat-linux@...el.com, kvm@...r.kernel.org,
        linux-crypto@...r.kernel.org, linux-pci@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/5] vfio/pci: add blocklist and disable qat

On Fri, Jul 10, 2020 at 04:48:07PM +0100, Christoph Hellwig wrote:
> On Wed, Jul 01, 2020 at 01:42:09PM +0100, Christoph Hellwig wrote:
> > On Wed, Jul 01, 2020 at 12:02:57PM +0100, Giovanni Cabiddu wrote:
> > > This patchset defines a blocklist of devices in the vfio-pci module and adds
> > > the current generation of Intel(R) QuickAssist devices to it as they are
> > > not designed to run in an untrusted environment.
> > 
> > How can they not be safe?  If any device is not safe to assign the
> > whole vfio concept has major issues that we need to fix for real instead
> > of coming up with quirk lists for specific IDs.
> 
> No answer yet:  how is this device able to bypass the IOMMU?  Don't
> we have a fundamental model flaw if a random device can bypass the
> IOMMU protection?  Except for an ATS bug I can't really think of a way
> how a device could bypass the IOMMU, and in that case we should just
> disable ATS.
Apologies.
This is specific to the QAT device and described in QATE-39220 in the
QAT release notes:
https://01.org/sites/default/files/downloads/336211-014-qatforlinux-releasenotes-hwv1.7_0.pdf
If a request with an address outside of the IOMMU domain attached to the
device is submitted, the device can lock up or induce a platform hang.

Regards,

-- 
Giovanni

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