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Message-Id: <20200713002512.28742-4-TheSven73@gmail.com>
Date: Sun, 12 Jul 2020 20:25:10 -0400
From: Sven Van Asbroeck <thesven73@...il.com>
To: shawnguo@...nel.org, s.hauer@...gutronix.de
Cc: Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-clk@...r.kernel.org
Subject: [PATCH v1 3/5] dt-bindings: imx6qdl-clock: add QuadPlus enet clocks
On the QuadPlus, hardware designers have improved the enet clocking.
Add these QuadPlus-specific clocks to the dt-bindings.
Signed-off-by: Sven Van Asbroeck <TheSven73@...il.com>
---
Tree: v5.8-rc4
To: Shawn Guo <shawnguo@...nel.org>
To: Sascha Hauer <s.hauer@...gutronix.de>
Cc: Pengutronix Kernel Team <kernel@...gutronix.de>
Cc: Fabio Estevam <festevam@...il.com>
Cc: NXP Linux Team <linux-imx@....com>
Cc: linux-kernel@...r.kernel.org
Cc: linux-arm-kernel@...ts.infradead.org
Cc: linux-clk@...r.kernel.org
Documentation/devicetree/bindings/clock/imx6q-clock.yaml | 2 ++
include/dt-bindings/clock/imx6qdl-clock.h | 5 ++++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml
index 92a8e545e212..ecd28403eeff 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml
@@ -34,6 +34,7 @@ properties:
- description: ckih1 clock input
- description: anaclk1 clock input
- description: anaclk2 clock input
+ - description: anaclk3 clock input
clock-names:
items:
@@ -42,6 +43,7 @@ properties:
- const: ckih1
- const: anaclk1
- const: anaclk2
+ - const: anaclk3
fsl,pmic-stby-poweroff:
$ref: /schemas/types.yaml#/definitions/flag
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index e20c43cc36f6..afc6b7b1e3e6 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -273,6 +273,9 @@
#define IMX6QDL_CLK_MMDC_P0_IPG 263
#define IMX6QDL_CLK_DCIC1 264
#define IMX6QDL_CLK_DCIC2 265
-#define IMX6QDL_CLK_END 266
+#define IMX6QDL_CLK_ENET_PAD 266
+#define IMX6QDL_CLK_ENET_PTP 267
+#define IMX6QDL_CLK_ANACLK3 268
+#define IMX6QDL_CLK_END 269
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.17.1
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