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Date: Mon, 13 Jul 2020 11:34:25 +0530 From: Vinod Koul <vkoul@...nel.org> To: Sivaprakash Murugesan <sivaprak@...eaurora.org> Cc: agross@...nel.org, bjorn.andersson@...aro.org, bhelgaas@...gle.com, robh+dt@...nel.org, kishon@...com, mturquette@...libre.com, sboyd@...nel.org, svarbanov@...sol.com, lorenzo.pieralisi@....com, p.zabel@...gutronix.de, mgautam@...eaurora.org, smuthayy@...eaurora.org, varada@...eaurora.org, linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org, Selvam Sathappan Periakaruppan <speriaka@...eaurora.org> Subject: Re: [PATCH 6/9] phy: qcom-qmp: Add compatible for ipq8074 pcie gen3 qmp phy On 05-07-20, 14:47, Sivaprakash Murugesan wrote: > ipq8074 has two pcie ports, one gen2 and one gen3 ports. with phy > support already available for gen2 pcie ports add support for pcie gen3 > port phy. > > Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@...eaurora.org> > Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@...eaurora.org> > Signed-off-by: Sivaprakash Murugesan <sivaprak@...eaurora.org> > --- > drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h | 137 ++++++++++++++++++++++++ > drivers/phy/qualcomm/phy-qcom-qmp.c | 172 +++++++++++++++++++++++++++++- > 2 files changed, 307 insertions(+), 2 deletions(-) > create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h > > diff --git a/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h > new file mode 100644 > index 000000000000..bb567673d9b5 > --- /dev/null > +++ b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h > @@ -0,0 +1,137 @@ > +/* SPDX-License-Identifier: GPL-2.0* Trailing * at the end, it would make sense to split the spdx and copyright parts to two single lines > @@ -2550,8 +2707,16 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) > > init.ops = &clk_fixed_rate_ops; > > - /* controllers using QMP phys use 125MHz pipe clock interface */ > - fixed->fixed_rate = 125000000; > + /* > + * controllers using QMP phys use 125MHz pipe clock interface unless > + * other frequency is specified in dts > + */ > + ret = of_property_read_u32(np, "clock-output-rate", > + (u32 *)&fixed->fixed_rate); is this cast required? > + if (ret) > + fixed->fixed_rate = 125000000; > + > + dev_info(qmp->dev, "fixed freq %lu\n", fixed->fixed_rate); debug? -- ~Vinod
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