lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Mon, 13 Jul 2020 14:10:03 +0800 From: Xu Yilun <yilun.xu@...el.com> To: mdf@...nel.org, linux-fpga@...r.kernel.org, linux-kernel@...r.kernel.org Cc: lgoncalv@...hat.com, trix@...hat.com, Matthew Gerlach <matthew.gerlach@...ux.intel.com>, Xu Yilun <yilun.xu@...el.com> Subject: [PATCH v2 2/2] fpga: dfl: fix bug in port reset handshake From: Matthew Gerlach <matthew.gerlach@...ux.intel.com> When putting the port in reset, driver must wait for the soft reset acknowledgment bit instead of the soft reset bit. Fixes: 47c1b19c160f (fpga: dfl: afu: add port ops support) Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com> Signed-off-by: Xu Yilun <yilun.xu@...el.com> Acked-by: Wu Hao <hao.wu@...el.com> Reviewed-by: Tom Rix <trix@...hat.com> --- v2: add Reviewed-by of Tom, no code change. --- drivers/fpga/dfl-afu-main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c index 7c84fee..753cda4 100644 --- a/drivers/fpga/dfl-afu-main.c +++ b/drivers/fpga/dfl-afu-main.c @@ -83,7 +83,8 @@ int __afu_port_disable(struct platform_device *pdev) * on this port and minimum soft reset pulse width has elapsed. * Driver polls port_soft_reset_ack to determine if reset done by HW. */ - if (readq_poll_timeout(base + PORT_HDR_CTRL, v, v & PORT_CTRL_SFTRST, + if (readq_poll_timeout(base + PORT_HDR_CTRL, v, + v & PORT_CTRL_SFTRST_ACK, RST_POLL_INVL, RST_POLL_TIMEOUT)) { dev_err(&pdev->dev, "timeout, fail to reset device\n"); return -ETIMEDOUT; -- 2.7.4
Powered by blists - more mailing lists