linux-kernel - Re: [PATCH] dt-bindings: devfreq: rk3399

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Mon, 13 Jul 2020 16:23:09 +0900
From:   Chanwoo Choi <cw00.choi@...sung.com>
To:     Enric Balletbo i Serra <enric.balletbo@...labora.com>,
        linux-kernel@...r.kernel.org
Cc:     Collabora Kernel ML <kernel@...labora.com>, dianders@...omium.org,
        heiko@...ech.de, maz@...nel.org, Rob Herring <robh@...nel.org>,
        Gaël PORTAY <gael.portay@...labora.com>,
        MyungJoo Ham <myungjoo.ham@...sung.com>,
        Kyungmin Park <kyungmin.park@...sung.com>,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        linux-pm@...r.kernel.org
Subject: Re: [PATCH] dt-bindings: devfreq: rk3399_dmc: Add rockchip,pmu
 phandle

Hi Enric,

On 7/9/20 6:05 PM, Enric Balletbo i Serra wrote:
> The Rockchip DMC (Dynamic Memory Interface) needs to access to the PMU
> general register files to know the DRAM type, so add a phandle to the
> syscon that manages these registers.
> 
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
> Reviewed-by: Chanwoo Choi <cw00.choi@...sung.com>
> Acked-by: Rob Herring <robh@...nel.org>
> Signed-off-by: Gaël PORTAY <gael.portay@...labora.com>
> Acked-by: MyungJoo Ham <myungjoo.ham@...sung.com>
> ---
> Following the discussion in [1] and after having [2] accepted, this
> patch is a RESEND of a patch [3] that has already all the acks but for
> some reason and my bad, I lost the tracking, didn't land. The patch adds
> documentation for an already property implemented in the driver, so
> resend the patch again. There is a slighty modification, the rockchip,pmu
> property has been moved to be optional as is not really required.
> 
> Thanks,
>   Enric
> 
> [1] https://protect2.fireeye.com/v1/url?k=0a124f1c-57c247d0-0a13c453-000babff3793-37ca8c47e6666c09&q=1&e=40f33cd6-b2d6-4de2-a309-fbf8645f89f9&u=https%3A%2F%2Flkml.org%2Flkml%2F2020%2F6%2F22%2F692
> [2] https://protect2.fireeye.com/v1/url?k=1aca44e8-471a4c24-1acbcfa7-000babff3793-6f0cff085cef3454&q=1&e=40f33cd6-b2d6-4de2-a309-fbf8645f89f9&u=https%3A%2F%2Flkml.org%2Flkml%2F2020%2F6%2F30%2F367
> [3] https://patchwork.kernel.org/patch/10901593/
> 
>  Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> index 0ec68141f85a..a10d1f6d85c6 100644
> --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> @@ -18,6 +18,8 @@ Optional properties:
>  			 format depends on the interrupt controller.
>  			 It should be a DCF interrupt. When DDR DVFS finishes
>  			 a DCF interrupt is triggered.
> +- rockchip,pmu:		 Phandle to the syscon managing the "PMU general register
> +			 files".
>  
>  Following properties relate to DDR timing:
>  
>

Applied it. Thanks.

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics